本文選題：60GHz + 多柵晶體管結(jié)構(gòu)��； 參考：《東南大學(xué)》2015年碩士論文

【摘要】：當(dāng)今社會(huì)的高速發(fā)展使得人們對(duì)短距離無(wú)線通信的數(shù)據(jù)傳輸速度提出了越來(lái)越高的要求。由于極大帶寬等一系列優(yōu)點(diǎn),60GHz頻段無(wú)線通信系統(tǒng)可以達(dá)到Gb/s的通信速度,這使它能夠比較好地應(yīng)用在短距離無(wú)線通信場(chǎng)合。然而,在這么高的頻段上,基于CMOS工藝的全集成收發(fā)系統(tǒng),特別是其中的功率放大器模塊設(shè)計(jì)難度很大。從文獻(xiàn)調(diào)研結(jié)果來(lái)看,功率合成技術(shù)和中和電容技術(shù)的使用提高了60GHz CMOS功率放大器的輸出功率和增益等性能。但是,在實(shí)際應(yīng)用當(dāng)中具有重要意義的線性度和功率回退效率卻還沒(méi)有取得大的發(fā)展,這為60GHz頻段的大規(guī)模應(yīng)用設(shè)置了障礙。面對(duì)以上挑戰(zhàn),本文在變壓器匹配和中和電容技術(shù)的基礎(chǔ)上進(jìn)行創(chuàng)新,在功率放大器設(shè)計(jì)中采用了一種新型的復(fù)合式結(jié)構(gòu)——多柵晶體管結(jié)構(gòu)。理論分析顯示,該結(jié)構(gòu)能在幾乎不改變整體電路功耗的前提下同時(shí)實(shí)現(xiàn)線性度和回退效率的提升,有效突破這兩個(gè)指標(biāo)的制約。為了驗(yàn)證這個(gè)結(jié)構(gòu)的實(shí)際效果,本文采用65nm CMOS工藝設(shè)計(jì)并實(shí)現(xiàn)了一款60GHz兩級(jí)差分功率放大器,芯片面積為0.49mm2。測(cè)試結(jié)果顯示,在1V的供電電壓之下,電路的靜態(tài)功耗為24mW。當(dāng)電路工作在54GHz時(shí),輸出飽和功率和1dB壓縮點(diǎn)分別達(dá)到了10.5dBm和7.62 dBm。與公開(kāi)文獻(xiàn)相比,這是同等功耗的電路中輸出功率性能最好的。與之對(duì)應(yīng),電路的最大效率和1dB壓縮時(shí)的效率分別為23.3%和16.98%,這也是目前已發(fā)表結(jié)果中較優(yōu)的。在51～56GHz的范圍內(nèi),1dB壓縮點(diǎn)處的效率均大于8%。
[Abstract]:With the rapid development of the society, the data transmission speed of short-range wireless communication is demanded more and more. Due to a series of advantages, such as the maximum bandwidth, the wireless communication system in the 60GHz band can achieve the communication speed of GB / s, which makes it suitable for short range wireless communication. However, in such a high frequency band, it is very difficult to design a fully integrated transceiver system based on CMOS technology, especially the power amplifier module. The results show that the use of power combination technology and neutralization capacitor technology can improve the output power and gain of 60GHz CMOS power amplifier. However, the linearity and power back efficiency, which are of great significance in practical applications, have not yet made great progress, which poses an obstacle to the large-scale application of the 60GHz band. Facing the above challenges, this paper innovates on the basis of transformer matching and neutralizing capacitor technology, and adopts a new compound structure, multi-gate transistor structure, in the design of power amplifier. Theoretical analysis shows that the proposed structure can achieve the improvement of linearity and recovery efficiency at the same time without changing the power consumption of the whole circuit effectively breaking through the constraints of these two indexes. In order to verify the practical effect of this structure, a 60GHz two-stage differential power amplifier is designed and implemented using 65nm CMOS technology. The chip area is 0.49mm ~ 2. The test results show that the static power consumption of the circuit is 24 MW at 1 V supply voltage. When the circuit operates at 54GHz, the output saturation power and 1dB compression point are 10.5dBm and 7.62dBmrespectively. Compared with the open literature, this is the best output power performance in circuits with equal power consumption. The maximum efficiency of the circuit and the efficiency of 1dB compression are 23. 3% and 16. 98% respectively. The efficiency of 1 dB compression point is greater than 8 in the range of 51 ~ 56 GHz.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN722.75

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