本文選題：三維集成電路 + 掃描樹�。� 參考：《合肥工業(yè)大學》2015年碩士論文

【摘要】：隨著三維集成電路(Three-Dimensional Integrated Circuits,3D-ICs)的不斷發(fā)展,測試在集成電路的實現(xiàn)過程中是必不可少的環(huán)節(jié)。基于掃描的可測試性設(shè)計(Design for Testability, DFT)的多掃描鏈設(shè)計改善了單掃描鏈設(shè)計的測試應(yīng)用時間,但其測試數(shù)據(jù)量并未減少,繼而提出掃描樹設(shè)計方法用來減少測試應(yīng)用時間及測試數(shù)據(jù)量。掃描鏈設(shè)計的測試應(yīng)用時間由最長的掃描鏈的長度決定的,掃描樹結(jié)構(gòu)降低了最長掃描鏈的長度,從而減少測試應(yīng)用時間和測試數(shù)據(jù)量。在三維集成電路的掃描樹設(shè)計過程中,一方面層與層間的掃描單元的連接需要硅通孔(Through Silicon Via, TSV),但目前制造工藝還不夠成熟,TSV制造成本較高。另一方面掃描樹的葉子節(jié)點需要連接到掃描輸出端口,決定了測試引腳的數(shù)量以及測試響應(yīng)數(shù)據(jù)量,故而為了降低三維集成電路的測試成本,本文就TSV數(shù)量及掃描樹的葉子節(jié)點數(shù)量這兩個因素,研究了以下兩種三維集成電路的掃描樹結(jié)構(gòu)：首先,提出一種在掃描樹的葉子節(jié)點數(shù)量約束下優(yōu)化TSV數(shù)量的三維集成電路單掃描樹設(shè)計方法。采用整數(shù)線性規(guī)劃(Integer Linear Programming, IL P)算法,構(gòu)建在不同的掃描樹葉子節(jié)點數(shù)的約束下最小化TSV數(shù)量的三維集成電路單掃描樹ILP模型。實驗表明,與已有的三維集成電路單掃描樹設(shè)計方法相比,在相同葉子節(jié)點數(shù)量的情況下,本文所提方法能夠有效地減少TSV數(shù)量。其次,為了進一步減少測試應(yīng)用時間,在單掃描樹設(shè)計的基礎(chǔ)上,構(gòu)建三維集成電路多掃描樹的ILP模型,并在TSV數(shù)量的約束下優(yōu)化多掃描樹的葉子節(jié)點數(shù)量。根據(jù)實驗結(jié)果分析,相比于單掃描樹結(jié)構(gòu),多掃描樹結(jié)構(gòu)的葉子節(jié)點數(shù)量最優(yōu)時與單掃描樹的葉子節(jié)點數(shù)相差不多,TSV數(shù)量成倍的增加了,但大大減少了多掃描樹的測試應(yīng)用時間。本文提出的單掃描樹結(jié)構(gòu)有效地減少了TSV數(shù)量,多掃描樹結(jié)構(gòu)有效地減少了葉子節(jié)點數(shù)量和測試應(yīng)用時間。
[Abstract]:With the development of Three-dimensional Integrated Circuits (3D-ICs), testing is an essential part in the implementation of integrated circuits. The design of multi-scan chain based on Design for Testability (DFT) improves the test application time of single scan chain design, but the amount of test data is not reduced. Then a scanning tree design method is proposed to reduce the test application time and test data. The test application time of scan chain design is determined by the length of the longest scan chain. The scan tree structure reduces the length of the longest scan chain, thus reducing the test application time and the amount of test data. In the process of scanning tree design of 3D integrated circuits, on the one hand, the connection between layers and layers requires through Silicon via (TSV), but at present the manufacturing process is not mature enough to produce TSV. On the other hand, the leaf nodes of the scan tree need to be connected to the scan output port, which determines the number of test pins and the amount of test response data. In this paper, the following two kinds of scanning tree structures of 3D integrated circuits are studied: firstly, the number of TSV and the number of leaf nodes of the scan tree are studied. A single scan tree design method for 3D integrated circuits is proposed to optimize the number of TSV under the constraint of the number of leaf nodes in the scan tree. An integer linear programming (IL P) algorithm is used to construct a single scan tree ILP model for 3D integrated circuits, which minimizes the number of TSV nodes under the constraints of the number of leaf nodes in different scan trees. The experimental results show that the proposed method can effectively reduce the number of TSV in the case of the same number of leaf nodes compared with the existing single scan tree design method for 3D integrated circuits. Secondly, in order to further reduce the test application time, the ILP model of 3D integrated circuit multi-scan tree is constructed on the basis of single scan tree design, and the number of leaf nodes of multi-scan tree is optimized under the constraint of TSV number. According to the experimental results, compared with the single scan tree structure, when the number of leaf nodes of the multi-scan tree structure is optimal, the number of TSV increases exponentially when the number of leaf nodes of the multi-scan tree is the same as that of the single scan tree. However, the test application time of multi-scan tree is greatly reduced. The single scan tree structure proposed in this paper can effectively reduce the number of TSV, and the multi-scan tree structure can effectively reduce the number of leaf nodes and test application time.
【學位授予單位】：合肥工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN402

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相關(guān)碩士學位論文 前2條

1 胡靜云;3D-ICs優(yōu)化TSV和葉子節(jié)點數(shù)量的掃描樹設(shè)計[D];合肥工業(yè)大學;2015年

2 康玉霞;門檻圖和擬門檻圖中的一些優(yōu)化問題[D];青島大學;2008年

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本文編號：2089404