本文選題：時域量化 + 逐次逼近�。� 參考：《電子科技大學(xué)》2015年碩士論文

【摘要】：隨著通信行業(yè)、多媒體技術(shù)和數(shù)字化設(shè)備的快速發(fā)展,ADC作為模擬世界和數(shù)字世界溝通的橋梁,其性能向高速、高精度、低功耗方向發(fā)展。深亞微米工藝下數(shù)字電路的優(yōu)勢在于高速、低功耗,因此將數(shù)字電路的優(yōu)勢應(yīng)用在模數(shù)轉(zhuǎn)換器的設(shè)計中更能夠使其適應(yīng)發(fā)展需求。本文采用55 nm CMOS工藝,通過對各種結(jié)構(gòu)ADC以及混合結(jié)構(gòu)ADC的優(yōu)缺點(diǎn)進(jìn)行研究和分析,設(shè)計了一款基于時域量化的10位100MS/s逐次逼近型ADC。首先,模擬電路的發(fā)展趨勢之一是改變信號的表征方式,為了實(shí)現(xiàn)信號的時域表征,本文詳細(xì)分析了時域量化的核心電路,包括電壓時間轉(zhuǎn)換器VTC、時間數(shù)字轉(zhuǎn)換器TDC。通過對這兩個核心電路的分析和比較提出了本文中采用的時域量化電路結(jié)構(gòu),其中VTC電路采用脈寬調(diào)制結(jié)構(gòu)實(shí)現(xiàn)了輸入信號軌到軌量化,TDC電路采用D觸發(fā)器型和延遲線型組成的混合型結(jié)構(gòu)實(shí)現(xiàn)了8位溫度計編碼輸出,編碼電路采用N中取1碼編碼方式實(shí)現(xiàn)了4位二進(jìn)制量化結(jié)果輸出以及DAC陣列開關(guān)相應(yīng)位控制編碼輸出。同時對該電路中存在的失配、誤差進(jìn)行了研究和分析,通過利用時域量化冗余位提出了一種電路自校正方式。其次,為了實(shí)現(xiàn)高速、低功耗的目的,本文中采樣開關(guān)采用柵壓自舉結(jié)構(gòu)保證采樣線性度,DAC陣列采用分段式電容分裂結(jié)構(gòu),減小了芯片面積和功耗,比較器采用低回踢噪聲鐘控比較器結(jié)構(gòu),并對比較器的失配進(jìn)行校正、對等效輸入噪聲的影響進(jìn)行分析。同時針對傳統(tǒng)逐次逼近寄存器電路中存在延遲過大難以實(shí)現(xiàn)高速工作的特點(diǎn)提出了一種新型的逐次逼近寄存器結(jié)構(gòu),該結(jié)構(gòu)采用鎖存器實(shí)現(xiàn)移位功能,有效提高了電路工作速度,同時降低功耗。最后,基于55 nm CMOS工藝完成各個關(guān)鍵單元電路以及整體基于時域量化SAR ADC性能仿真驗證。為了更好地與實(shí)際結(jié)果相符,在仿真過程中對關(guān)鍵電路以及關(guān)鍵節(jié)點(diǎn)添加寄生參數(shù)。仿真結(jié)果表明:在采樣頻率為100MHz,輸入信號頻率為22.65625MHz的條件下,ADC的信號噪聲失真比SNDR為61.1070dB,無雜散動態(tài)范圍SFDR為71.0713dB,有效位ENOB為9.8583位,優(yōu)值FoM為39.2fJ/conversation-step,該性能滿足設(shè)計要求。本文中所設(shè)計的ADC在1.2V的電源電壓下功耗為3.65mW。
[Abstract]:With the rapid development of multimedia technology and digital equipment, ADC, as a bridge between analog world and digital world, is developing to high speed, high precision and low power consumption. The advantage of digital circuit in deep submicron technology lies in its high speed and low power consumption. Therefore, the advantage of digital circuit can be applied to the design of A / D converter to meet the needs of development. In this paper, the advantages and disadvantages of various ADC and hybrid ADC are studied and analyzed in 55nm CMOS technology. A 10-bit ADCs successive approximation based on time-domain quantization is designed. Firstly, one of the development trends of analog circuits is to change the signal representation. In order to realize the time domain representation, the core circuits of time domain quantization are analyzed in detail in this paper, including voltage time converter VTC and time digital converter TDC. Based on the analysis and comparison of the two core circuits, the time-domain quantization circuit structure used in this paper is proposed. The VTC circuit uses pulse width modulation structure to realize the input signal rail to rail quantization TDC circuit using the mixed structure of D flip-flop and delay line to realize 8-bit thermometer coding output. The 4-bit binary quantization result output and the DAC array switch corresponding bit control coding output are realized by using the 1-code encoding mode of N in the coding circuit. At the same time, the mismatch and error in the circuit are studied and analyzed, and a circuit self-tuning method is proposed by using redundant bits in time domain quantization. Secondly, in order to achieve the purpose of high speed and low power consumption, the sampling switch in this paper adopts the gate voltage bootstrap structure to ensure the sampling linearity degree DAC array to adopt the segmented capacitor split structure, which reduces the chip area and the power consumption. The comparator adopts the structure of low return kick noise clock controlled comparator, corrects the mismatch of the comparator, and analyzes the effect of equivalent input noise. At the same time, a new structure of successive approximation register is proposed, which uses latch to realize shift function, aiming at the characteristic that the delay is too big to work at high speed in the traditional successive approximation register circuit. The circuit speed is improved and the power consumption is reduced. Finally, every key cell circuit is completed based on 55nm CMOS process, and the performance of SAR ADC based on time domain quantization is verified by simulation. In order to better agree with the actual results, parasitic parameters are added to the key circuits and key nodes in the simulation process. The simulation results show that when the sampling frequency is 100 MHz and the input signal frequency is 22.65625 MHz, the signal noise distortion ratio of ADC is 61.1070dB, the SFDR is 71.0713dB, the effective bit ENOB is 9.8583 bits, and the excellent value FoM is 39.2 f / conversation step. The performance meets the design requirements. The ADC designed in this paper has a power consumption of 3.65 MW at 1.2V power supply voltage.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN792

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