本文選題：FPGA + EDA�。� 參考：《安徽大學(xué)》2015年碩士論文

【摘要】：隨著電子技術(shù)和信息科學(xué)的快速發(fā)展,鎖相環(huán)技術(shù)在突破了很多技術(shù)困難的同時(shí),其應(yīng)用領(lǐng)域也在不斷的擴(kuò)大,從原先在航天領(lǐng)域的應(yīng)用,如今,鎖相環(huán)已深入軍事、醫(yī)療、工業(yè)設(shè)計(jì)等諸多領(lǐng)域,目前,鎖相環(huán)已經(jīng)成為大規(guī)模集成電路、片上系統(tǒng)等高質(zhì)量電子設(shè)備中不可或缺的模塊。數(shù)字鎖相環(huán)的出現(xiàn),使鎖相環(huán)的性能飛速提升,它很好地克服了模擬鎖相環(huán)遇到的直流部件飽和、零點(diǎn)漂移以及需要進(jìn)行初始校準(zhǔn)等一系列的問題。隨著集成電路技術(shù)的日益精進(jìn),全數(shù)字鎖相環(huán)(ADPLL)相繼問世,這種鎖相環(huán)各個(gè)模塊的結(jié)構(gòu)全部由數(shù)字電路組成,并且具備實(shí)時(shí)處理能力,以及具有抗干擾性強(qiáng)、體積小和可靠性高等優(yōu)點(diǎn)。鑒于此,論文設(shè)計(jì)了一種增減量可變計(jì)數(shù)式全數(shù)字鎖相環(huán)的結(jié)構(gòu),并對該鎖相環(huán)進(jìn)行了電路設(shè)計(jì)和仿真分析。論文研究的主要工作如下：(1)對鎖相環(huán)各部件的結(jié)構(gòu)與性能進(jìn)行了系統(tǒng)分析和研究,提出了基于增減量可變計(jì)數(shù)式全數(shù)字鎖相環(huán)結(jié)構(gòu)設(shè)計(jì)方案；(2)對全數(shù)字鎖相環(huán)的各模塊進(jìn)行了詳細(xì)的結(jié)構(gòu)設(shè)計(jì)與電路設(shè)計(jì),并且進(jìn)行了仿真綜合；(3)基于上述各個(gè)模塊的電路設(shè)計(jì)和仿真,進(jìn)而實(shí)現(xiàn)了整體結(jié)構(gòu)設(shè)計(jì)與對比仿真分析。從仿真結(jié)果得出,此改進(jìn)型全數(shù)字鎖相環(huán)具有鎖定速度快、易于集成及控制靈活等優(yōu)點(diǎn)。
[Abstract]:With the rapid development of electronic technology and information science, phase locked loop (PLL) technology has broken through a lot of technical difficulties, and its application fields have also been continuously expanded. From the original application in the space field, now PLL has been deeply used in military and medical treatment. At present, phase locked loop (PLL) has become an indispensable module in high quality electronic devices such as large scale integrated circuits, on-chip systems and so on. The appearance of digital phase-locked loop (DPLL) makes the performance of PLL improve rapidly. It overcomes a series of problems such as DC component saturation zero drift and initial calibration of analog PLL. With the development of integrated circuit technology, all digital phase-locked loop (ADPLL) has come out one after another. The structure of each module of this kind of PLL is composed of digital circuit, and it has real-time processing ability and strong anti-jamming ability. Small size and high reliability and other advantages. In view of this, this paper designs a structure of all digital PLL with variable increment and decrease quantity, and carries on the circuit design and simulation analysis to the PLL. The main work of this paper is as follows: (1) the structure and performance of PLL components are systematically analyzed and studied, and a scheme of all-digital PLL structure design based on variable count is proposed. (2) the structure design and circuit design of all digital PLL modules are carried out in detail, and the simulation synthesis is carried out. (3) the circuit design and simulation based on the above modules are implemented, and the overall structure design and comparative simulation analysis are realized. The simulation results show that the improved all-digital PLL has the advantages of fast locking speed, easy integration and flexible control.
【學(xué)位授予單位】：安徽大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN911.8;TN791

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本文編號：2072769