本文選題：單粒子瞬態(tài) + 單粒子多瞬態(tài)��； 參考：《國防科學技術大學》2015年碩士論文

【摘要】：隨著中國綜合國力的進一步提升,航天航空器材和武器裝備對國產抗輻射芯片的需求越來越迫切�？馆椛浼呻娐泛洼椛湫难芯课絹碓蕉嗟膶W者們加入其中,同時也成為了該領域研究的重點課題之一。隨著納米CMOS集成電路的不斷發(fā)展,半導體器件的輻射效應特性也發(fā)生著多方面的變化,其中以單粒子瞬態(tài)尤為明顯。到納米工藝下,單粒子瞬態(tài)(SET)已經成為了輻射電路中系統(tǒng)軟錯誤出現(xiàn)的主要來源,同時也是新納米工藝下集成電路抗輻射加固的研究重點。在納米CMOS集成電路中,器件的特征尺寸更小、集成密度更大、節(jié)點相距更近。這使得單個高能粒子的入射可能導致多個節(jié)點的電荷收集,使SET的產生機理與以往的研究相比會出現(xiàn)許多新的情況,SET在傳播中也隨之出現(xiàn)一些新的現(xiàn)象。單粒子導致的多節(jié)點電荷共享現(xiàn)象,將可能出現(xiàn)單粒子多瞬態(tài)(SEMT)和單粒子脈沖窄化(SET Quenching),這些在65nm CMOS集成電路中已成為普遍現(xiàn)象。在新工藝節(jié)點下,單粒子多瞬態(tài)的研究工作變得日益重要,研究價值也越發(fā)的明顯。本文將針對SEMT的試驗測試技術展開一系列的研究工作,解決了新工藝節(jié)點下SEMT試驗表征的技術問題。本文提出了一種新型單粒子多瞬態(tài)測試系統(tǒng),并且在65nm工藝下設計了測試芯片,通過重離子輻射試驗證明了此測試系統(tǒng)在SEMT試驗研究方面的可行性,在解決SEMT試驗表征技術問題方面是一個創(chuàng)新。關于SEMT測試系統(tǒng)的研究,本文做了一些具體研究工作,并取得了一定的研究成果:⑴提出了一種SEMT測量電路。本文在單鏈SET測量技術的研究基礎之上,提出了一種新型SEMT測量電路。此測量電路既保證了單個SET的測量精度,又實現(xiàn)了多SET的同時捕獲,實現(xiàn)了SEMT的高精度自觸發(fā)掃描捕獲。這種SEMT測量電路對時序控制要求嚴格,并且還進行了抗輻射加固設計。⑵設計了新的轟擊單元。以往的SET研究都是以反相器鏈作為被測電路,根據不同的研究目的在版圖和電路方面做相應的處理。為了將PMOS器件和NMOS器件中的SEMT分別表征,本文設計了P-hit和N-hit轟擊單元;為了研究源極注入效應在多節(jié)點電荷共享收集中的作用,提出了改進型的P-hit和N-hit轟擊單元。⑶提出了一種SEMT被測電路結構。依據以往的研究經驗,提出了一種縱向交錯布局的多短鏈SEMT被測電路結構。試驗結果表明,該電路結構既保證了SEMT產生的合理性,又保證了單個SET測量的精確性。⑷實現(xiàn)了SEMT測試芯片,并設計了地面輻射試驗測試系統(tǒng)。將研究提出的SEMT測量電路和被測電路在65nm體硅CMOS工藝下實現(xiàn)了SEMT測試芯片,并且成功流片。在以往的輻射試驗研究基礎之上,針對SEMT測試芯片的輻射試驗設計了具體的試驗測試系統(tǒng),并完成了一次重離子輻射試驗。試驗結果表明:此SEMT測試系統(tǒng)完全能夠實現(xiàn)納米CMOS電路中SEMT的試驗表征,這將為SEMT的研究提供新的試驗方法,為進一步深入研究納米電路中單粒子瞬態(tài)提供了有效地研究手段和科學地試驗依據。
[Abstract]:With the further improvement of China's comprehensive national strength, the demand of aerospace equipment and weapons to domestic radiation chips is becoming more and more urgent. Research on integrated circuits and radiation effects has attracted more and more scholars to join, and it has also become one of the key topics in this field. With the nano CMOS integrated circuit With the continuous development of the semiconductor devices, there are many changes in the radiation effects of semiconductor devices, in which the single particle transient is particularly obvious. Under the nanotechnology, the single particle transient (SET) has become the main source of the soft error in the radiation circuit, and is also the focus of the research on the anti radiation reinforcement of the integrated circuits under the new nanotechnology. In nanoscale CMOS integrated circuits, the characteristic size of the device is smaller, the integration density is larger, the node distance is closer. This makes the incidence of a single high-energy particle may lead to the collection of the charge of multiple nodes, so that there will be a lot of new situations in the generation mechanism of the SET and the previous research, and the SET will also appear some new phenomena in the transmission. The phenomenon of multi node charge sharing caused by sub nodes will be likely to appear single particle multiple transient (SEMT) and single particle pulse narrowing (SET Quenching). These have become a common phenomenon in the 65nm CMOS integrated circuit. Under the new technology node, the research work of single particle and multi transient is becoming more and more important and the research value is more obvious. This paper will be aimed at SEMT A series of research work has been carried out to solve the technical problems of SEMT test characterization under the new process node. A new single particle multi transient test system is proposed in this paper, and the test chip is designed under the 65nm process. The feasibility of the test system in the SEMT test research is proved by the heavy ion radiation test. It is an innovation in solving the technical problems of SEMT test characterization. On the research of SEMT testing system, this paper has done some specific research work and obtained some research results: (1) a kind of SEMT measurement circuit is proposed. Based on the study of single strand SET measurement technology, a new type of SEMT measurement circuit is proposed. The measurement circuit not only ensures the measurement accuracy of a single SET, but also realizes the simultaneous capture of multiple SET, and realizes the high precision self triggered scan capture of SEMT. This SEMT measurement circuit is strict with the timing control, and has also carried out the design of anti radiation reinforcement. (2) the new bombardment unit is designed. The former SET research has been measured as the inverter chain. In order to characterize the PMOS and the SEMT in the NMOS devices, the P-hit and the N-hit bombardment units are designed in this paper. In order to study the role of the source injection effect in the collection of multi node charge sharing, an improved P-hit and N-hit bombardment unit is proposed. A kind of SEMT measured circuit structure is presented. Based on previous research experience, a multi short chain SEMT circuit structure with longitudinal staggered layout is proposed. The experimental results show that the circuit structure not only ensures the rationality of the SEMT production, but also ensures the accuracy of the single SET measurement. 4. The SEMT test chip is realized and the ground radiation test is designed. The SEMT measurement circuit and the measured circuit proposed in this paper have realized the SEMT test chip under the 65nm body silicon CMOS technology and the successful flow sheet. On the basis of the previous radiation test, the specific test system was designed for the radiation test of the SEMT test chip, and a heavy ion radiation test was completed and the test junction was completed. The results show that the SEMT test system can fully realize the test characterization of SEMT in the nano CMOS circuit. This will provide a new test method for the study of SEMT, and provide effective research means and scientific test basis for further study of single particle transient in nanoscale circuits.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN40

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