本文選題：IPSec協(xié)議 + SoC��； 參考：《計(jì)算機(jī)工程與設(shè)計(jì)》2017年05期

【摘要】：為達(dá)到IPSec實(shí)現(xiàn)的高速性、靈活性以及安全性,設(shè)計(jì)一個(gè)IPSec加速SoC。引入高速PCIE接口突破主機(jī)與SoC通信速度瓶頸;采取多核設(shè)計(jì)技術(shù)和層次化存儲(chǔ)結(jié)構(gòu),構(gòu)建以交叉存儲(chǔ)為主的高速數(shù)據(jù)交換區(qū)和以郵箱為主的引擎間狀態(tài)通信區(qū);采用指令級(jí)并行和流水線并行技術(shù),對(duì)IPSec協(xié)議中算法進(jìn)行多核映射。實(shí)驗(yàn)結(jié)果表明,該SoC對(duì)于IPSec中典型分組密碼算法AES的吞吐率可達(dá)1Gbps,對(duì)于認(rèn)證算法SM3可達(dá)2Gbps,較好地滿足了高速網(wǎng)絡(luò)處理需求。
[Abstract]:In order to achieve the high speed, flexibility and security of IPSec implementation, an IPSec accelerated SoC is designed. High speed PCIE interface is introduced to break through the bottleneck of communication speed between host computer and SoC, and multi-core design technology and hierarchical storage structure are adopted to construct high speed data exchange area based on cross storage and state communication area between engines based on mailbox. Instruction level parallelism and pipeline parallelism are used to map the algorithms in IPSec protocol. Experimental results show that the throughput of the SoC to AES, a typical block cipher algorithm in IPSec, can reach 1Gbpsand to the authentication algorithm SM3 up to 2Gbpss.This SoC can better meet the needs of high-speed network processing.
【作者單位】： 信息工程大學(xué);
【分類號(hào)】：TN402
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本文編號(hào)：2047752