本文選題：OTP邏輯陣列 + 邏輯功能　； 參考：《電子科技大學(xué)》2015年碩士論文

【摘要】：隨著時(shí)代的發(fā)展,信息安全越來(lái)越受到重視,一次性可編程邏輯陣列在科學(xué)前進(jìn)的道路中扮演了越來(lái)越重要的角色。OTP邏輯陣列具有較高可靠性,極強(qiáng)的抗輻照能力,可以廣泛的運(yùn)用于涉及到軍事、航空航天等保密性極高和外界環(huán)境較為復(fù)雜的領(lǐng)域。本文的OTP邏輯陣列通過(guò)了測(cè)試,為將來(lái)設(shè)計(jì)出高性能的OTP FPGA提供參考。本文通過(guò)理論分析和測(cè)試,采用0.18μm CMOS的工藝,把實(shí)驗(yàn)室自主設(shè)計(jì)的OTP位元單元應(yīng)用于電路,設(shè)計(jì)出了一款256bit的邏輯陣列。設(shè)計(jì)工作主要包括位元單元結(jié)構(gòu)的設(shè)計(jì),外圍電路的設(shè)計(jì),整體版圖的設(shè)計(jì)以及流片后測(cè)試結(jié)果分析。本文首先介紹了OTP位元的結(jié)構(gòu)以及其擊穿原理,緊接著介紹了位元的工作機(jī)制。外圍電路主要包括OTP邏輯陣列的各個(gè)功能模塊實(shí)現(xiàn)電路:編程模塊、讀測(cè)試模塊和功能實(shí)現(xiàn)模塊,文中對(duì)各個(gè)模塊中的關(guān)鍵電路的功能、原理進(jìn)行了闡述,其中編程電路中采用了兩級(jí)電荷泵的結(jié)構(gòu),產(chǎn)生可控制的編程外加高壓,防止對(duì)芯片內(nèi)部單元誤擊穿和避免對(duì)常壓電路造成干擾;介紹了讀電路中的兩極DICE鎖存結(jié)構(gòu)和靈敏放大器的工作原理,保證正確快速的從位元單元中讀取數(shù)據(jù)并且保證數(shù)據(jù)的穩(wěn)定性;同時(shí)還闡述了邏輯功能單元中的CLB單元是如何實(shí)現(xiàn)邏輯功能,并且對(duì)各個(gè)電路進(jìn)行功能仿真,給出了仿真結(jié)果。在設(shè)計(jì)實(shí)現(xiàn)的過(guò)程中,設(shè)計(jì)考慮了芯片面積、I/O端口和模塊的布局、電路的布線問(wèn)題,從電源規(guī)劃到布局到布線,詳細(xì)闡述了設(shè)計(jì)過(guò)程。設(shè)計(jì)時(shí)除了考慮面積的大小外,還需要考慮各個(gè)可制造性的問(wèn)題,盡量?jī)?yōu)化設(shè)計(jì),避免各個(gè)不良效應(yīng)。通過(guò)物理驗(yàn)證DRC和LVS后,提取相應(yīng)的寄生參數(shù),得到實(shí)際設(shè)計(jì)后的各個(gè)精確參數(shù),實(shí)現(xiàn)后仿真,仿真的結(jié)果基本達(dá)到預(yù)期要求。流片回來(lái)后,通過(guò)自主搭建的平臺(tái),分兩步對(duì)芯片進(jìn)行測(cè)試,從基本的讀寫(xiě)功能到邏輯功能進(jìn)行測(cè)試,基本功能均能實(shí)現(xiàn),達(dá)到了芯片的設(shè)計(jì)期望。
[Abstract]:With the development of the times, more and more attention has been paid to the information security. The one-off programmable logic array has played a more and more important role in the progress of science. OTP logic array has high reliability and strong anti-irradiation ability. Can be widely used in military, aerospace and other areas of high confidentiality and complex external environment. The OTP logic array in this paper has passed the test, which provides a reference for designing high performance OTP FPGA in the future. In this paper, a 256bit logic array is designed by theoretical analysis and test, using 0.18 渭 m CMOS technology. The design work mainly includes the design of the bit unit structure, the peripheral circuit design, the design of the whole layout and the analysis of the test results after the flow sheet. This paper first introduces the structure of OTP bit and its breakdown principle, then introduces the working mechanism of OTP bit. The peripheral circuit mainly includes the realization circuit of each function module of OTP logic array: programming module, reading and testing module and function realization module. The function and principle of the key circuit in each module are expounded in this paper. The structure of the two-stage charge pump is used in the programming circuit, which produces the controllable programming and high voltage to prevent the breakdown of the internal unit of the chip and to avoid the interference to the normal voltage circuit. This paper introduces the bipolar DICE latch structure and the working principle of the sensitive amplifier in the reading circuit to ensure the correct and fast reading of data from the bit unit and the stability of the data. At the same time, how the CLB unit in the logic function unit realizes the logic function, and carries on the function simulation to each circuit, gives the simulation result. In the process of design and implementation, the layout of the chip area I / O port and module, the wiring of the circuit are considered, from the power source planning to the layout to the wiring, the design process is described in detail. In addition to considering the size of the area, it is necessary to consider the problems of manufacturability and optimize the design so as to avoid the adverse effects. After physical verification of DRC and LVS, the parasitic parameters are extracted, and the precise parameters are obtained. The simulation results basically meet the expected requirements. After the chip comes back, the chip is tested in two steps through the self-built platform, from the basic reading and writing function to the logic function, and the basic function can be realized, which meets the design expectation of the chip.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN791

【相似文獻(xiàn)】

相關(guān)期刊論文 前8條

1 楊盛國(guó);指導(dǎo)學(xué)生制作OTP單片機(jī)型脈搏心率計(jì)[J];福建師大福清分校學(xué)報(bào);2003年S1期

2 沈熙磊;;上海宏力半導(dǎo)體0.18微米低本高效OTP制程成功量產(chǎn)[J];半導(dǎo)體信息;2011年02期

3 袁蕊林;陳奕含;羅前;李曼;李平;;一種OTP存儲(chǔ)器高速讀出機(jī)制的設(shè)計(jì)[J];微電子學(xué)與計(jì)算機(jī);2012年01期

4 袁蕊林;陳志鈞;張頡夫;陳奕含;;一種OTP存儲(chǔ)器片上時(shí)序信號(hào)產(chǎn)生電路的設(shè)計(jì)[J];電子元器件應(yīng)用;2011年12期

5 黎旺星;OTP單片機(jī)的多次編程方法[J];電子世界;2002年02期

6 丁錦滔;;PIC12C5xx單片機(jī)編程器和OTP的再燒寫(xiě)[J];電子制作;2005年08期

7 ;安森美半導(dǎo)體180nm工藝技術(shù)嵌入Sidense的1T-OTP存儲(chǔ)器[J];電子設(shè)計(jì)工程;2011年08期

8 ;[J];;年期

相關(guān)會(huì)議論文 前1條

1 楊盛國(guó);;指導(dǎo)學(xué)生制作OTP單片機(jī)型脈搏心率計(jì)[A];福建師大福清分校2003年會(huì)議論文匯編[C];2003年

相關(guān)重要報(bào)紙文章 前1條

1 江蘇 任曉方;P87LPC76×系列OTP單片機(jī)重復(fù)編程法[N];電子報(bào);2001年

相關(guān)碩士學(xué)位論文 前3條

1 吳欣昱;OTP邏輯陣列設(shè)計(jì)實(shí)現(xiàn)研究[D];電子科技大學(xué);2015年

2 周知名;OTP存儲(chǔ)器設(shè)計(jì)研究[D];浙江大學(xué);2010年

3 馮寧波;基于ARM的OTP芯片燒寫(xiě)測(cè)試設(shè)備的設(shè)計(jì)與實(shí)現(xiàn)[D];蘇州大學(xué);2013年

，

本文編號(hào)：2044343