發(fā)布時(shí)間：2018-06-18 13:13

  本文選題：氮化鎵 + MOSFET　； 參考：《大連理工大學(xué)》2015年博士論文

【摘要】：GaN半導(dǎo)體具有禁帶寬度大、臨界擊穿電場(chǎng)高、載流子飽和漂移速度高等優(yōu)異特性,是制造大功率、高頻、高溫等器件的理想材料。與AlGaN/GaN HEMT相比,GaN MOSFET具有柵漏電流小、柵電壓工作范圍大、不需額外柵極驅(qū)動(dòng)電路及容易制作成增強(qiáng)型器件等優(yōu)點(diǎn),故而廣受關(guān)注。然而受限于實(shí)際p-GaN晶體質(zhì)量較差、本征氧化層禁帶寬度較窄等問(wèn)題,GaN MOSFET較難通過(guò)傳統(tǒng)的Si MOSFET工藝實(shí)現(xiàn)。采用AlGaN/GaN異質(zhì)結(jié)結(jié)構(gòu)雖能實(shí)現(xiàn)GaN MOSFET,但其柵區(qū)溝槽干法刻蝕的損傷會(huì)使器件界面態(tài)密度增大、閾值電壓負(fù)漂,最終導(dǎo)致器件性能下降。此外,干法刻蝕工藝還會(huì)使器件溝道尺寸發(fā)生變化,導(dǎo)致器件遷移率評(píng)價(jià)出現(xiàn)較大誤差。因此,如何實(shí)現(xiàn)GaN MOSFET、怎樣去除溝槽干法刻蝕損傷、如何正確評(píng)價(jià)器件的溝道遷移率等都是需要研究的問(wèn)題。針對(duì)以上問(wèn)題,本文對(duì)AlGaN/GaN異質(zhì)結(jié)上GaN MOSFET進(jìn)行了器件和工藝設(shè)計(jì),對(duì)其中關(guān)鍵的柵區(qū)溝槽干法刻蝕等工藝進(jìn)行了優(yōu)化,提出了改進(jìn)的溝道遷移率評(píng)價(jià)新方法。此外利用干法刻蝕損傷機(jī)理,開(kāi)發(fā)了三種新型低溫及非合金GaN、AlGaN上的歐姆接觸工藝,并通過(guò)這些工藝實(shí)現(xiàn)了先柵結(jié)構(gòu)GaN MOSFET、自對(duì)準(zhǔn)結(jié)構(gòu)GaN MOSFET及AlGaN/GaN HEMT等新型器件。這些器件中都利用了干法刻蝕工藝,形成溝槽柵或低溫歐姆接觸。干法刻蝕工藝貫穿了本文的整個(gè)研究,這也是論文題目的由來(lái)。論文主要研究?jī)?nèi)容及結(jié)果如下：(1) AlGaN/GaN異質(zhì)結(jié)結(jié)構(gòu)的GaN MOSFET的版圖工藝設(shè)計(jì)及溝槽干法刻蝕的研究。采用L-Edit設(shè)計(jì)了AlGaN/GaN異質(zhì)結(jié)上的GaN MOSFET版圖,并對(duì)其進(jìn)行了工藝實(shí)現(xiàn)。同時(shí)對(duì)GaN MOSFET中關(guān)鍵的溝槽干法刻蝕工藝進(jìn)行了預(yù)備實(shí)驗(yàn),通過(guò)原子力顯微鏡(AFM)對(duì)不同干法刻蝕阻擋層、刻蝕氣體流量、反應(yīng)室壓強(qiáng)等條件下刻蝕出的GaN樣品進(jìn)行了掃描,研究了其溝槽形貌、表面粗糙度、刻蝕速率等情況。實(shí)驗(yàn)結(jié)果表明,采用光刻膠作刻蝕阻擋層時(shí),阻擋層側(cè)墻對(duì)刻蝕離子的反射作用,會(huì)導(dǎo)致溝槽出現(xiàn)側(cè)墻處過(guò)度刻蝕現(xiàn)象,采用Si02作阻擋層則不會(huì)出現(xiàn)此現(xiàn)象。此外采用較高刻蝕氣體流量時(shí),刻蝕面會(huì)出現(xiàn)顆粒狀突起使其表面變粗糙。當(dāng)反應(yīng)室的壓強(qiáng)較大時(shí),干法刻蝕過(guò)程中的沉積效應(yīng)將會(huì)增強(qiáng),刻蝕速率顯著降低且有副產(chǎn)物沉積于刻蝕面。最終實(shí)驗(yàn)初步確定了溝槽干法刻蝕的優(yōu)選工藝條件,即采用Si02作為干法刻蝕阻擋層、在較小的氣體流量(3 sccm)與反應(yīng)室壓強(qiáng)(0.25 Pa)條件下,干法刻蝕后的樣品的溝槽形貌較好,表面平整粗糙度較小且副產(chǎn)物在表面沉積較少。(2) GaN MOSFET溝道遷移率評(píng)價(jià)方法的研究與改進(jìn)。在條形的GaN MOSFET器件中發(fā)現(xiàn)了因?yàn)椴涣紙?chǎng)隔離現(xiàn)象導(dǎo)致的平行溝道現(xiàn)象,它會(huì)使得器件的溝道遷移率被高估。在對(duì)溝道長(zhǎng)度較小的器件進(jìn)行評(píng)價(jià)時(shí)由于溝槽過(guò)刻的現(xiàn)象會(huì)導(dǎo)致制作出來(lái)的器件柵長(zhǎng)大于版圖的設(shè)計(jì)柵長(zhǎng),使得器件的溝道遷移率值被低估。本文通過(guò)實(shí)驗(yàn)證實(shí)并分析了以上現(xiàn)象,提出了四種在溝道尺寸有變化情況下正確提取GaN MOSFET遷移率的改進(jìn)方法。此外本章也就GaN MOS系統(tǒng)的界面態(tài)密度評(píng)價(jià)方法做了簡(jiǎn)單說(shuō)明,針對(duì)其中一些問(wèn)題提出了有效的改進(jìn)措施。實(shí)驗(yàn)結(jié)果顯示這四種方法不僅可以準(zhǔn)確提取出器件溝道遷移率值,也可以估算因?yàn)闇喜圻^(guò)度刻蝕所帶來(lái)的溝道長(zhǎng)度的變化量。用這些改進(jìn)方法所得到的溝道遷移率值和長(zhǎng)溝道環(huán)形器件中遷移率標(biāo)準(zhǔn)值一致,表明這些方法合理有效。(3) AlGaN/GaN異質(zhì)結(jié)結(jié)構(gòu)GaN MOSFET的工藝依賴性研究。實(shí)驗(yàn)中具體研究了溝槽干法刻蝕阻擋層、刻蝕氣體種類及步驟、刻蝕Bias功率、柵氧化層種類及其厚度等對(duì)GaN MOSFET器件性能的影響,結(jié)合XPS等手段對(duì)導(dǎo)致器件閾值電壓負(fù)漂的干法刻蝕損傷進(jìn)行了分析評(píng)價(jià),并通過(guò)電學(xué)測(cè)試的方法定量研究了MOS界面的等效電荷密度。針對(duì)這些問(wèn)題開(kāi)發(fā)了氮等離子體(N+)及氨水處理(NH4OH)方法,有效修復(fù)和去除了溝槽干法刻蝕損傷。實(shí)驗(yàn)表明采用Si02作干法刻蝕阻擋層、SiCl4做刻蝕氣體、較小的干法刻蝕Bias功率、硅烷基PECVD制作的柵Si02層是比較優(yōu)化的工藝。此外,通過(guò)XPS及電學(xué)測(cè)試發(fā)現(xiàn)在MOS界面處存在1012 q/cm2數(shù)量級(jí)的正電荷,它們很可能是由溝槽干法刻蝕過(guò)程中的干法刻蝕損傷引起。通過(guò)NH4OH處理,可以有效的去除干法刻蝕損傷,得到溝道遷移率為148.12 cm2/Vs的增強(qiáng)型GaN MOSFET。相應(yīng)的MOS二極管中提取到的界面態(tài)密度在EC-ET為0.2到0.6 eV的可測(cè)范圍內(nèi)約為3×1011 cm-2eV-1，較干法刻蝕后的界面態(tài)密度值顯著下降。(4)三種新型低溫及非合金GaN、AlGaN上歐姆接觸新工藝的開(kāi)發(fā)與其在新型先柵結(jié)構(gòu)GaN MOSFET、自對(duì)準(zhǔn)結(jié)構(gòu)GaN MOSFET及AlGaN/GaN HEMT中的應(yīng)用研究。首先利用干法刻蝕損傷輔助工藝開(kāi)發(fā)了一系列GaN、AlGaN上非合金和低溫歐姆接觸工藝,并對(duì)其中機(jī)理進(jìn)行了分析解釋,對(duì)制作出的歐姆接觸進(jìn)行了評(píng)價(jià)。結(jié)合比較獨(dú)特的雙層膠光刻工藝,開(kāi)發(fā)制作了新型先柵結(jié)構(gòu)GaN MOSFET、自對(duì)準(zhǔn)結(jié)構(gòu)的GaN MOSFET和AlGaN/GaN HEMT,并對(duì)其進(jìn)行了電學(xué)評(píng)價(jià),對(duì)一些不理想的因素進(jìn)行了分析,提出了相應(yīng)的改進(jìn)措施。結(jié)果表明采用非合金歐姆接觸工藝的先柵結(jié)構(gòu)GaN MOSFET性能優(yōu)異,其溝道遷移率達(dá)到了163.8 cm2/Vs。采用低溫歐姆工藝的自對(duì)準(zhǔn)結(jié)構(gòu)的GaN MOSFET和AlGaN/GaN HEMT可以工作,且制作工藝可以進(jìn)一步優(yōu)化來(lái)使器件的性能更加優(yōu)異。
[Abstract]:GaN semiconductor has high band gap width, high critical breakdown electric field and high carrier saturation drift speed, which is the ideal material for high power, high frequency and high temperature devices. Compared with AlGaN/GaN HEMT, GaN MOSFET has small gate leakage current and large grid voltage working range, without additional gate drive circuit and easy to be made into enhanced type Because of the poor quality of the p-GaN crystal and the narrow band gap of the intrinsic oxidation layer, the GaN MOSFET is more difficult to be realized by the traditional Si MOSFET process. The AlGaN/GaN heterostructure can realize GaN MOSFET, but the damage of the dry etching of the gate groove will increase the density of the interface state. The negative drift of threshold voltage leads to the decrease of device performance. In addition, the dry etching process will also change the channel size of the device, which leads to the large error in the evaluation of the mobility of the device. Therefore, how to realize the GaN MOSFET, how to remove the dry etching damage of the groove and how to correctly evaluate the channel mobility of the device are all needed to be studied. In view of the above problems, the design of GaN MOSFET on AlGaN/GaN heterojunction is designed, and the key technology of dry etching of the gate groove is optimized, and a new method of improving the channel migration rate is proposed. In addition, three new types of low temperature and unalloyed GaN, AlGaN are developed by using the mechanism of the dry etching damage. The ohmic contact process has been carried out. Through these processes, the first gate structure GaN MOSFET, the self aligned GaN MOSFET and AlGaN/GaN HEMT devices are used. These devices all use the dry etching process to form the groove gate or low temperature ohmic contact. The dry etching process runs through the whole study of this article, which is the origin of the thesis. The main contents and results of this thesis are as follows: (1) the layout process design of GaN MOSFET for AlGaN/GaN heterostructure and the study of trench dry etching. The GaN MOSFET layout of AlGaN/GaN heterojunction was designed with L-Edit, and the process was realized. The key groove dry etching process in GaN MOSFET was prepared. The experiment was conducted by atomic force microscopy (AFM) to scan the GaN samples etched by different dry etching barrier layers, etching gas flow and reaction chamber pressure, and the groove morphology, surface roughness and etching rate were studied. The reflection effect will lead to excessive etching in the side wall of the groove, and the phenomenon will not appear by using Si02 as the barrier layer. In addition, when the high etching gas flow is used, the etching surface will appear granular protuberance and make the surface roughness. When the pressure of the reaction chamber is larger, the deposition effect in the dry etching process will be enhanced and the etching rate will be increased. In the final experiment, the optimum technological conditions for the dry etching of the grooves were determined, that is, the Si02 was used as the dry etching barrier. Under the condition of the smaller gas flow (3 SCCM) and the pressure of the reaction chamber (0.25 Pa), the groove shape of the sample after the dry etching was better and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was less. The side products are less deposited on the surface. (2) the study and improvement of the GaN MOSFET channel mobility evaluation method. The parallel channel phenomenon caused by the bad field isolation is found in the bar shaped GaN MOSFET device, which makes the channel mobility of the device overestimated. The phenomenon will lead to the design of the gate length larger than the layout, which makes the channel mobility of the device underestimated. In this paper, the above phenomena are confirmed and analyzed by experiments. Four kinds of methods to correct the transfer rate of GaN MOSFET under the change of channel size are proposed. In addition, this chapter is also on the bounds of the GaN MOS system. The surface density evaluation method is simply explained, and some effective improvement measures are put forward for some of the problems. The experimental results show that these four methods can not only accurately extract the mobility of the channel channel, but also estimate the variation of channel length caused by the excessive groove etching. The mobility values are in accordance with the standard mobility standard values in the long channel ring devices, indicating that these methods are reasonable and effective. (3) the process dependence of the AlGaN/GaN heterostructure GaN MOSFET. In the experiment, the dry etching barrier layer, the types and steps of the etching gas, the etching Bias power, the type and thickness of the gate oxide layer and the thickness of GaN MOSF are studied in the experiment. The effects of the performance of ET devices are analyzed by means of XPS and other means. The equivalent charge density of the MOS interface is quantitatively studied by electrical testing. The nitrogen plasma (N+) and ammonia water treatment (NH4OH) method is developed for these problems, and the groove is effectively repaired and removed. Dry etching damage. The experiment shows that Si02 is used as a dry etching barrier layer, SiCl4 is etching gas, small dry etching of Bias power, and the grid Si02 layer produced by silane PECVD is a relatively optimized process. In addition, there is a 1012 q/cm2 order of positive charge at the MOS interface by XPS and electrical testing. They are likely to be trench dry. Dry etching damage in the process of etching can be caused by NH4OH treatment, and the dry etching damage can be effectively removed. The interface state density extracted from the MOS diode of the enhanced GaN MOSFET. with a channel mobility of 148.12 cm2/Vs is about 3 x 1011 cm-2eV-1 in the range of 0.2 to 0.6 eV, compared with the dry etching. The density of the interface states decreased significantly. (4) the development of three new cryogenic and unalloyed GaN, AlGaN ohm contact new processes and its application in the new gate structure GaN MOSFET, the self aligned GaN MOSFET and AlGaN/GaN HEMT. First, a series of GaN, non alloy and low temperature on AlGaN were developed by the dry etching damage auxiliary technology. The ohm contact process was analyzed and the mechanism was analyzed. The ohm contact was evaluated. Combined with a unique double layer photolithography process, a new gate structure GaN MOSFET, GaN MOSFET and AlGaN/GaN HEMT with self aligned structure were developed and the electrical evaluation was carried out, and some undesirable factors were carried out. The results show that the first gate structure of the non alloy ohm contact process GaN MOSFET has excellent performance, the channel migration rate is 163.8 cm2/Vs., and the self aligned GaN MOSFET and AlGaN/GaN HEMT with low temperature ohm process can work, and the fabrication process can be further optimized to make the device. The performance is better.
【學(xué)位授予單位】：大連理工大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN386

【相似文獻(xiàn)】

相關(guān)期刊論文 前10條

1 周榮春,張海霞,郝一龍;微加工干法刻蝕工藝模擬工具的研究現(xiàn)狀[J];微納電子技術(shù);2003年Z1期

2 敬小成,黃美淺,姚若河;攜帶氣體對(duì)二氧化硅干法刻蝕的影響[J];微電子學(xué);2005年05期

3 王沖;郝躍;馮倩;郭亮良;;氮化鎵干法刻蝕研究進(jìn)展[J];半導(dǎo)體技術(shù);2006年06期

4 葛強(qiáng);;硅的干法刻蝕簡(jiǎn)介[J];集成電路應(yīng)用;2008年04期

5 張欽亮;蘇靜洪;王謨;平志韓;雍春娥;祝啟蒙;金志杰;;一種干法刻蝕機(jī)的新型裝載腔設(shè)計(jì)[J];制造技術(shù)與機(jī)床;2013年03期

6 劉明大;激光輔助干法刻蝕的新進(jìn)展[J];半導(dǎo)體光電;1986年02期

7 李曉明;;干法刻蝕技術(shù)的進(jìn)展[J];半導(dǎo)體情報(bào);1987年04期

8 朱洪亮;干法刻蝕Ⅲ—Ⅴ族化合物半導(dǎo)體材料的最新進(jìn)展[J];科學(xué)通報(bào);1989年22期

9 江澤流;;微細(xì)制版中的干法刻蝕技術(shù)研究[J];電子工藝技術(shù);1991年05期

10 李祥;干法刻蝕鋁合金引線產(chǎn)生的后腐蝕及其對(duì)策[J];微電子技術(shù);1996年01期

相關(guān)會(huì)議論文 前6條

1 楊霏;周瑞;李亮;馮震;李效白;潘宏菽;蔡樹(shù)軍;;碳化硅器件制備中干法刻蝕工藝的研究[A];第十六屆全國(guó)半導(dǎo)體物理學(xué)術(shù)會(huì)議論文摘要集[C];2007年

2 陳磊;張靖;毛謙;;ICP干法刻蝕技術(shù)在Ⅲ-Ⅴ族化合物中的應(yīng)用[A];武漢市第二屆學(xué)術(shù)年會(huì)、通信學(xué)會(huì)2006年學(xué)術(shù)年會(huì)論文集[C];2006年

3 張沛元;郭浩;張雄;崔一平;;藍(lán)光LED的Si基圖形化襯底制備技術(shù)[A];2012（杭州）中國(guó)長(zhǎng)三角照明科技論壇論文集[C];2012年

4 栗銳;王義;林罡;陳堂勝;;干法柵挖槽GaAs HFET功率管[A];2010’全國(guó)半導(dǎo)體器件技術(shù)研討會(huì)論文集[C];2010年

5 賴建軍;趙悅;柯才軍;周宏;易新建;翁雪濤;熊平;;硅衍射微透鏡陣列的制作技術(shù)研究[A];2004全國(guó)圖像傳感器技術(shù)學(xué)術(shù)交流會(huì)議論文集[C];2004年

6 江忠永;李書(shū)文;張昊翔;;干法和濕法圖形化藍(lán)寶石襯底在GaN基LED上的應(yīng)用[A];2012（杭州）中國(guó)長(zhǎng)三角照明科技論壇論文集[C];2012年

相關(guān)重要報(bào)紙文章 前1條

1 吳建新;在微電子領(lǐng)域奮力攀登[N];大眾科技報(bào);2000年

相關(guān)博士學(xué)位論文 前2條

1 王青鵬;干法刻蝕輔助型GaN MOSFET的器件工藝及電學(xué)特性研究[D];大連理工大學(xué);2015年

2 曹萌;干法刻蝕和離子注入影響Ⅲ-Ⅴ族半導(dǎo)體量子阱發(fā)光特性研究[D];中國(guó)科學(xué)院研究生院（上海微系統(tǒng)與信息技術(shù)研究所）;2007年

相關(guān)碩士學(xué)位論文 前6條

1 李賀;基于金屬氧化物半導(dǎo)體的電子器件集成[D];山東大學(xué);2016年

2 張新言;干法刻蝕制程工藝及相關(guān)缺陷的分析和改善[D];上海交通大學(xué);2009年

3 邱鵬;C_4F_6在130nm產(chǎn)品中接觸孔/通孔干法刻蝕工藝中的應(yīng)用[D];上海交通大學(xué);2008年

4 張超;寬帶隙氧化鋅和氧化鎵的干法刻蝕研究[D];大連理工大學(xué);2014年

5 王笑龍;納米多孔氮化鎵制備及氮化鎵干法刻蝕損傷回復(fù)研究[D];中國(guó)科學(xué)院研究生院（上海微系統(tǒng)與信息技術(shù)研究所）;2006年

6 徐煒;0.18微米側(cè)壁（Spacer）干法刻蝕工藝的開(kāi)發(fā)與優(yōu)化[D];復(fù)旦大學(xué);2008年

，

本文編號(hào)：2035606