發(fā)布時(shí)間：2018-06-12 03:55

  本文選題：薄膜晶體管 + D觸發(fā)器　； 參考：《華南理工大學(xué)學(xué)報(bào)(自然科學(xué)版)》2017年03期

【摘要】：設(shè)計(jì)了一個(gè)基于Pseudo-CMOS邏輯門(mén)的低功耗異步復(fù)位D觸發(fā)器電路.該D觸發(fā)器全部由n型a-IGZO TFTs(薄膜晶體管)構(gòu)成,采用動(dòng)態(tài)負(fù)載替代Pseudo-CMOS拓?fù)渲械亩䴓O管連接負(fù)載,通過(guò)減少電路導(dǎo)通的概率來(lái)降低靜態(tài)功耗.電路的輸出級(jí)為鎖存器,通過(guò)反饋通路減少由動(dòng)態(tài)負(fù)載造成的輸出擺幅降低對(duì)延遲的影響.將該D觸發(fā)器應(yīng)用于環(huán)行移位寄存器的設(shè)計(jì)中,結(jié)果表明,該觸發(fā)器電路可有效降低或非門(mén)邏輯電路中的靜態(tài)功耗.
[Abstract]:A low power asynchronous reset D flip-flop circuit based on Pseudo-CMOS logic gate is designed. The D-flip-flop consists of n-type a-IGZO TFTs (thin film transistor). The dynamic load is used to replace the diode connection load in Pseudo-CMOS topology, and the static power consumption is reduced by reducing the probability of circuit turn-on. The output stage of the circuit is a latch, and the effect of the output swing reduction caused by the dynamic load on the delay is reduced by the feedback path. The D flip-flop is applied to the design of the cyclic shift register. The results show that the flip-flop circuit can effectively reduce the static power consumption in the non-gate logic circuit.
【作者單位】： 華南理工大學(xué)電子與信息學(xué)院;
【基金】：國(guó)家自然科學(xué)基金資助項(xiàng)目(61274085) 廣東省科技計(jì)劃項(xiàng)目(2015B090909001)~~
【分類號(hào)】：TN783
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本文編號(hào)：2008225