本文選題：鎖相環(huán) + 高速接口��； 參考：《山東大學》2015年碩士論文

【摘要】：現(xiàn)今高速接口系統(tǒng)設(shè)計通常都需要時鐘來使系統(tǒng)內(nèi)的各模塊電路實現(xiàn)同步運行和確定系統(tǒng)間的通信協(xié)議。鎖相環(huán)電路作為現(xiàn)代高速接口系統(tǒng)中的重要模塊之一,產(chǎn)生時鐘來使系統(tǒng)內(nèi)的各模塊電路得以運行。本文基于CSMC0.18umCMOS工藝,面向高速接口中的HDMI2.0接口標準,設(shè)計了一款鎖相環(huán)電路,輸入?yún)⒖紩r鐘經(jīng)過該鎖相環(huán)電路后生成25 MHz～600MHz的八個等間距的時鐘信號。本文研究了鎖相環(huán)的基本概念和電荷泵鎖相環(huán)的各組成模塊的原理；使用Cadence軟件設(shè)計了電荷泵鎖相環(huán)各模塊電路,包括鑒頻鑒相器、電荷泵、環(huán)路濾波器、壓控振蕩器、分頻器和LDO電路。設(shè)計鑒頻鑒相器時考慮了死區(qū)問題,加入延時單元；采用了電流轉(zhuǎn)向電荷泵,由兩路互補的開關(guān)和單位增益運算放大器構(gòu)成,可以改善電荷共享效應(yīng)的影響；采用四級差分型的環(huán)形壓控振蕩器,以滿足八個等間距的時鐘信號的要求；設(shè)計了一個高速的TSPC型二分頻電路和一個五分頻電路級聯(lián)的十分頻器；因鎖相環(huán)對電源波動十分敏感,設(shè)計了一款LDO專門用來為其他模塊提供純凈和穩(wěn)定的電源電壓,將3.3V輸入電源電壓轉(zhuǎn)換為1.8V穩(wěn)定的輸出電壓。最后進行了仿真驗證,結(jié)果表明該鎖相環(huán)電路能實現(xiàn)預(yù)期的功能。本文設(shè)計的電荷泵鎖相環(huán)電路以最新的HDMI2.0接口標準為依據(jù),具有很好的應(yīng)用價值和研究意義。
[Abstract]:Nowadays, the design of high speed interface system usually needs a clock to realize the synchronous operation of each module circuit in the system and to determine the communication protocol between the systems. As one of the most important modules in modern high speed interface system, PLL circuit generates clock to make each module circuit run. Based on CSMC 0.18um CMOS technology and HDMI 2.0 interface standard in high speed interface, a phase locked loop (PLL) circuit is designed in this paper. After the input reference clock is passed through the PLL circuit, eight equal spacing clock signals of 25 MHz are generated. In this paper, the basic concept of PLL and the principle of every module of CPPLL are studied, and the circuits of CPPLL are designed with Cadence software, including frequency discriminator, charge pump, loop filter, voltage-controlled oscillator, etc. Frequency divider and LDO circuit. In the design of the phase discriminator, the dead-time problem is considered, the delay unit is added, the current steering charge pump is adopted, which is composed of two complementary switches and the unit gain operational amplifier, which can improve the effect of charge sharing. A four-stage differential ring voltage-controlled oscillator is used to meet the requirements of eight equal spacing clock signals, and a high speed TSPC two-frequency divider and a five-frequency divider cascade are designed. Because PLL is very sensitive to power fluctuation, a LDO is designed to provide pure and stable power supply voltage for other modules. The 3.3V input power supply voltage is converted to 1.8V stable output voltage. Finally, the simulation results show that the PLL circuit can achieve the desired function. The charge-pump PLL circuit designed in this paper is based on the latest HDMI 2.0 interface standard and has good application value and research significance.
【學位授予單位】：山東大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN402

【參考文獻】

相關(guān)期刊論文 前1條

1 代國定,莊奕琪,劉鋒;超低壓差CMOS線性穩(wěn)壓器的設(shè)計[J];電子器件;2004年02期

，

本文編號：1988143