本文選題：通信基帶 + OVM��； 參考：《西安電子科技大學》2016年碩士論文

【摘要】：隨著集成電路的高速發(fā)展,芯片設(shè)計的規(guī)模越來越大,功能越來越復(fù)雜,導致在電路設(shè)計階段出現(xiàn)缺陷的可能性越來越高,這就對驗證提出了更高的要求。此外隨著芯片的應(yīng)用領(lǐng)域越來越廣,對設(shè)計安全性的要求也越來越高,為了避免設(shè)計漏洞可能造成的嚴重后果,驗證的充分性就顯得尤為重要。市場對芯片產(chǎn)品的更新?lián)Q代也越來越快,在大規(guī)模的集成電路開發(fā)的前端設(shè)計流程中,驗證工作已經(jīng)占了總工作量的百分之七十左右。因此,設(shè)計高效可行的驗證方法對芯片的設(shè)計與應(yīng)用具有重要意義。本文重點研究數(shù)字集成電路設(shè)計中通信基帶芯片模塊級驗證平臺的設(shè)計。在OVM驗證方法學的基礎(chǔ)上,使用System Verilog語言,結(jié)合實際應(yīng)用需求,針對SOC芯片中DebugTrace系統(tǒng),設(shè)計出重用性好、可靠性高、功能具有模塊化的驗證平臺。同時,在本文所設(shè)計的驗證平臺還對Module TB的結(jié)構(gòu)進行了改進,論文根據(jù)平臺的實際功能,將ovm_env劃分成top_env,src_env和fmt_env三個功能,在SUB TB中將所有traceport的接口信號例化,并連接至DUT(待測設(shè)計,Design Under Test),通過monitor和scoreboard作檢測對比,驗證該模塊在整個DebugTrace系統(tǒng)中是否工作正常。SUB TB的工作均在同一TB下完成,而非以往,不同traceport有各自的TB驗證各自的功能,簡化了TB結(jié)構(gòu),完成了模塊級的驗證工作。最終通過一個具體的Trace,即RFIF,驗證了本文的驗證方法縮短了驗證時間,實現(xiàn)了功能覆蓋測試點的全覆蓋,提升了驗證平臺的復(fù)用性、靈活性、穩(wěn)定性。論文最后在DebugTrace系統(tǒng)的編譯環(huán)境下,使用基于Makefile配置文件的驗證方法,對RFIF進行驗證仿真,并對仿真結(jié)果進行分析,新方法的仿真時間為11443ns,較之前的17042ns有了明顯的縮短,同時功能覆蓋率也達到了100%的預(yù)期效果。說明本文方法行之有效,達到了設(shè)計指標。
[Abstract]:With the rapid development of integrated circuits, the scale of chip design becomes larger and larger, and the functions become more and more complex, which leads to the higher possibility of defects in the circuit design stage, which puts forward higher requirements for verification. In addition, with the increasing application of the chip, the design security requirements are becoming higher and higher. In order to avoid the serious consequences of the design vulnerability, it is particularly important to verify the adequacy of the chip. The replacement of chip products in the market is also becoming faster and faster. In the front-end design process of large-scale integrated circuit development, verification has accounted for about 70% of the total workload. Therefore, the design of efficient and feasible verification method is of great significance to the design and application of the chip. This paper focuses on the design of communication baseband chip module level verification platform in digital integrated circuit design. On the basis of OVM verification methodology, a verification platform with good reusability, high reliability and modularized function is designed for DebugTrace system in SOC chip by using System Verilog language and practical application requirements. At the same time, the structure of Module TB has been improved in the verification platform designed in this paper. According to the actual function of the platform, the ovm_env is divided into three functions, named topSnvsrcenv and fmt_env, and the interface signals of all traceport are exemplified in SUB TB. It is connected to DUTs (Design Under Test Unit). Through monitor and scoreboard, it is verified that the module works properly in the whole DebugTrace system. SUBTB is completed under the same TB, but different traceport has its own function of TB verification. The TB structure is simplified and the module level verification is completed. Finally, through a specific Trace-RFIFI, the verification method of this paper shortens the verification time, realizes the full coverage of the functional coverage test points, and improves the reusability, flexibility and stability of the verification platform. Finally, under the compiling environment of DebugTrace system, the verification method based on Makefile configuration file is used to verify and simulate RFIF, and the simulation results are analyzed. The simulation time of the new method is 11443ns, which is obviously shorter than that of 17042ns before. At the same time, the functional coverage also reached 100% of the expected effect. It shows that the method is effective and reaches the design target.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2016
【分類號】：TN407

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本文編號：1984302