本文選題：軟件無線電 + 數(shù)字下變頻��； 參考：《西華師范大學(xué)》2017年碩士論文

【摘要】：針對目前電子技術(shù)和通訊技術(shù)等領(lǐng)域內(nèi)信號提取過程中存在的噪音與混疊的弊病,本課題改進(jìn)了一種數(shù)字下變頻系統(tǒng),通過其在FPGA芯片上增加級數(shù)并降低階數(shù)來增強系統(tǒng)抗混疊度的設(shè)計方式,不僅降低了設(shè)計的復(fù)雜程度、節(jié)約了設(shè)計成本及能耗,且由于FPGA硬件平臺的可重構(gòu)能力,使得數(shù)字下變頻系統(tǒng)(DDC)實時更新靈活。本課題以信號的基本采樣理論為基礎(chǔ),研究基于FPGA的多通道DDC設(shè)計方案。課題中針對過程中所運用信號處理基本算法、各部分實現(xiàn)方法進(jìn)行深入分析。采用自上而下分析方法,詳盡研究下變頻系統(tǒng)當(dāng)中重要組成部分,如數(shù)字控制振蕩器(NCO)、混頻器以及梳狀濾波器組、半帶濾波器以及有限沖激響應(yīng)濾波器等重要構(gòu)造�；贔PGA平臺對系統(tǒng)中各個子系統(tǒng)分別進(jìn)行調(diào)試與仿真,使用QuartusⅡ軟件中VHDL語言編程與IP核宏模塊的調(diào)用方式設(shè)計數(shù)控振蕩器模塊與混頻器模塊,運用Matlab中的FDAtool軟件包與IP核結(jié)合方式設(shè)計多種濾波器組合模塊,最終將各個子模塊調(diào)用到Matlab軟件中進(jìn)行整體調(diào)試,驗證設(shè)計目標(biāo)。針對每個模塊分別展開分析,NCO運用坐標(biāo)旋轉(zhuǎn)(CORDIC)算法實現(xiàn),信號生成快、占用資源少;混頻器模塊運用乘法算法原理,簡單、芯片引腳利用率降低;梳狀濾波器組對原本單一的梳狀濾波器(CIC)進(jìn)行補充,運用延遲與移位語句降低對邏輯門的需求而有限沖激響應(yīng)濾波器模塊對信道中的信號進(jìn)行整形,采用直線型與窗函數(shù)兩種方法對比來選擇最優(yōu)處理方式。系統(tǒng)測試表明,該系統(tǒng)可以完整實現(xiàn)數(shù)字下變頻的功能,能不失真地還原輸入信號。NCO采用迭代相加方案,降低芯片引腳實際利用率;CIC組合濾波器增進(jìn)阻帶衰減與此同時使帶內(nèi)容差降低到0.5dB以內(nèi);運用窗函數(shù)形式設(shè)計FIR濾波器經(jīng)Matlab測試能濾除混疊噪音、整形濾波,還原有效信號。整體測試效果滿足設(shè)計要求,達(dá)到設(shè)計目標(biāo)。
[Abstract]:In view of the disadvantages of noise and aliasing in the signal extraction process in the fields of electronic technology and communication technology, a digital downconversion system is improved in this paper. The design method of enhancing the anti-aliasing degree of the system by increasing the series and decreasing the order on the FPGA chip not only reduces the complexity of the design, but also saves the design cost and energy consumption, and because of the reconfigurable ability of the FPGA hardware platform. The DDC system is flexible to update in real time. Based on the basic sampling theory of signal, the design scheme of multi-channel DDC based on FPGA is studied in this paper. In this paper, the basic algorithm of signal processing used in the process is analyzed in detail. Using top-down analysis method, the important components of down-conversion system, such as digital controlled oscillator (DCO), mixer and comb filter bank, half-band filter and finite impulse response filter, are studied in detail. Each subsystem of the system is debugged and simulated based on FPGA platform. The NC oscillator module and mixer module are designed by using VHDL language programming in Quartus 鈪，

本文編號：1981447