本文選題：逐次逼近型ADC + 40nm工藝　； 參考：《電子科技大學(xué)》2015年碩士論文

【摘要】：逐次逼近型SAR ADC(successive approximation A/D converter)具有結(jié)構(gòu)簡(jiǎn)單、節(jié)省功耗的特點(diǎn),因此隨著工藝尺寸的減小,SAR ADC相對(duì)于其他ADC架構(gòu)(例如pipelined ADC)逐漸顯示出兩大優(yōu)勢(shì):(1)組成SAR ADC大部分電路為數(shù)字電路,在深亞微米及納米級(jí)工藝下,數(shù)字電路可以達(dá)到更快的速度。(2)SAR ADC不需要一個(gè)高增益高帶寬的運(yùn)放來(lái)獲取足夠的線性度。一個(gè)高性能的運(yùn)放不僅要占用較大的功耗,同時(shí)還要受到短溝道效應(yīng)和電源電壓的限制。這些SAR ADC的優(yōu)勢(shì)使其在低壓低功耗應(yīng)用領(lǐng)域逐漸受到設(shè)計(jì)者的青睞。本文基于40nm CMOS工藝,對(duì)逐次逼近型SAR ADC的系統(tǒng)架構(gòu)和關(guān)鍵單元電路進(jìn)行了深入的研究和分析,并設(shè)計(jì)了一個(gè)12位1MS/s的SAR ADC。首先,為了獲得較優(yōu)的系統(tǒng)架構(gòu),本文首先分析了DAC中影響系統(tǒng)性能的一些因素,主要包括電容失配,分段結(jié)構(gòu),寄生電容等。根據(jù)分析和推導(dǎo)結(jié)果,選取了全差分tri-level結(jié)構(gòu)為DAC的基本架構(gòu)。根據(jù)工藝廠商提供的單位電容值和失配的關(guān)系對(duì)DAC進(jìn)行了MATLAB建模,選取了合適的單位電容值和分段結(jié)構(gòu),以保證在滿足精度要求的前提下,盡量減小采樣電容的值和功耗。然后著重研究了柵壓自舉開(kāi)關(guān)、動(dòng)態(tài)比較器和時(shí)序控制電路。由于本文的設(shè)計(jì)目標(biāo)為12位的ADC,用傳統(tǒng)的latch作比較器難以達(dá)到想要的精度。因?yàn)閯?dòng)態(tài)比較器與傳統(tǒng)的靜態(tài)比較器相比,不需要偏置電路,沒(méi)有靜態(tài)功耗,因此比較器選用了一個(gè)兩級(jí)的動(dòng)態(tài)比較器,第一級(jí)為動(dòng)態(tài)預(yù)放大,第二級(jí)為latch。著重分析了影響動(dòng)態(tài)比較器噪聲的主要因素,并分析了減小動(dòng)態(tài)比較器噪聲的方法。最后,分析了深亞微米及納米工藝下的STI效應(yīng)和WEP效應(yīng),并介紹了在電路和版圖中解決STI效應(yīng)和WEP效應(yīng)的方法�；�40nm CMOS工藝完成了各個(gè)關(guān)鍵單元電路以及整體SAR ADC版圖的實(shí)現(xiàn),并對(duì)整個(gè)12位1MS/s SAR ADC進(jìn)行了后仿驗(yàn)證。后仿結(jié)果表明:在采樣頻率為1MHz,輸入信號(hào)頻率為456KHz的條件下,ADC的信號(hào)噪聲失真比(SNDR)為73.77dB,無(wú)雜散動(dòng)態(tài)范圍(SFDR)為81.99dB,有效位數(shù)(ENOB)為11.96位。另外,所設(shè)計(jì)的ADC的功耗為0.67mW,版圖面積為0.169mm2。
[Abstract]:Successive approximation SAR ADC(successive approximation A / D converters have the advantages of simple structure and low power consumption. Therefore, with the decrease of process size, SAR ADC is composed of digital circuits compared with other ADC architectures (such as pipelined ADC1). In deep submicron and nanoscale processes, the digital circuit can achieve a faster speed. The ADC does not require a high gain and high bandwidth operational amplifier to obtain sufficient linearity. A high performance operational amplifier not only takes up large power consumption, but also is limited by short channel effect and power supply voltage. The advantages of these SAR ADC make it more and more popular with designers in low-voltage and low-power applications. Based on 40nm CMOS process, the system architecture and key unit circuits of successive approximation SAR ADC are studied and analyzed in this paper, and a 12-bit 1MS/s SAR SAR ADC is designed. First of all, in order to obtain a better system architecture, this paper first analyzes some factors that affect the system performance in DAC, including capacitor mismatch, segmented structure, parasitic capacitance and so on. According to the results of analysis and derivation, the fully differential tri-level structure is selected as the basic structure of DAC. According to the relationship between unit capacitance value and mismatch provided by process manufacturer, the MATLAB model of DAC is built, and the appropriate unit capacitance value and segment structure are selected to ensure that the value and power consumption of the sample capacitance can be minimized under the premise of satisfying the precision requirement. Then, the gate voltage bootstrap switch, dynamic comparator and timing control circuit are studied. Because the design goal of this paper is 12-bit latch, it is difficult to achieve the desired precision by using traditional latch as comparator. Compared with the traditional static comparator, the dynamic comparator has no bias circuit and no static power consumption, so the comparator selects a two-stage dynamic comparator, the first stage is dynamic preamplifier, and the second stage is latch. The main factors influencing the noise of dynamic comparator are analyzed, and the methods to reduce the noise of dynamic comparator are analyzed. Finally, the STI effect and WEP effect in deep submicron and nanometer process are analyzed, and the methods to solve STI effect and WEP effect in circuit and layout are introduced. The realization of each key unit circuit and the whole SAR ADC layout based on 40nm CMOS process is completed, and the 12 bit 1MS/s SAR ADC is verified by post-simulation. The post-simulation results show that when the sampling frequency is 1 MHz and the input signal frequency is 456KHz, the signal noise distortion ratio (SNDR) is 73.77 dB, the non-spurious dynamic range is 81.99 dB, and the effective bit number is 11.96 bits. In addition, the power consumption of the designed ADC is 0.67 MW and the layout area is 0.169 mm ~ 2.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN792

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 陳宏銘;郝躍國(guó);趙龍;程玉華;;An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement[J];Journal of Semiconductors;2013年09期

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本文編號(hào)：1976529