本文選題：數(shù)據(jù)包解析器 + CAM　； 參考：《電子科技大學(xué)》2015年碩士論文

【摘要】：近十年來網(wǎng)絡(luò)技術(shù)高速發(fā)展,給大家?guī)肀憷耐瑫r(shí),越來越多設(shè)備對路由器和交換機(jī)的性能以及可配置性提出了迫切需求。為了建立高效、穩(wěn)定和安全的網(wǎng)絡(luò)系統(tǒng),網(wǎng)絡(luò)設(shè)備生產(chǎn)商們更加關(guān)注于其設(shè)備的通用性和擴(kuò)展性,而這些無一例外的體現(xiàn)在了對數(shù)據(jù)包進(jìn)行解析,識別包頭和提取數(shù)據(jù)上,以支持對數(shù)據(jù)包的分類和安全功能。過去對于數(shù)據(jù)包的解析相對比較簡單,然而隨著MPLS(Multi-Protocol Label Switching)和802.1Q等夾層協(xié)議的加入,使得高速的解析數(shù)據(jù)包越發(fā)的困難。通常在沒有夾層協(xié)議的情況下,數(shù)據(jù)包解析器的吞吐率可達(dá)到10-100Gbps。然而,在夾層協(xié)議下,數(shù)據(jù)包解析器的吞吐率卻急劇下降。因此在高速路由器或交換機(jī)中,數(shù)據(jù)包的解析就成了潛在的瓶頸。為了解決上述問題,要求更加高效的實(shí)現(xiàn)解決方案。本文將圍繞靈活的高速網(wǎng)絡(luò)數(shù)據(jù)包解析器的架構(gòu)設(shè)計(jì)展開研究。首先,本文研究并歸納整理了近幾年國內(nèi)外對高速網(wǎng)絡(luò)數(shù)據(jù)包解析器架構(gòu)設(shè)計(jì)的方法,對比分析了各種高速網(wǎng)絡(luò)數(shù)據(jù)包解析器架構(gòu)設(shè)計(jì)的優(yōu)缺點(diǎn)。其次,本文提出了一種新穎的靈活數(shù)據(jù)包解析器架構(gòu)。通過采用流水線技術(shù),CAM(Content Addressable Memory)和LUT(Look Up Table)的聯(lián)合存儲(chǔ)查詢結(jié)構(gòu),該架構(gòu)能夠自適應(yīng)新的數(shù)據(jù)包頭(包含夾層協(xié)議和隧道以太網(wǎng)幀等)。另外,本文還提出了一種離線映射算法,通過離線映射,該架構(gòu)能夠在一個(gè)流水級中一次性解析多個(gè)協(xié)議組合,并擁有非常高的靈活性和吞吐率。最后,本文選擇Altera公司的FPGA開發(fā)平臺,對該架構(gòu)進(jìn)行了實(shí)現(xiàn)。根據(jù)實(shí)際網(wǎng)絡(luò)中存在的以太網(wǎng)幀,對數(shù)據(jù)包解析器架構(gòu)進(jìn)行了性能測試,并給出了硬件資源,工作時(shí)鐘頻率等信息。相對已有的數(shù)據(jù)包解析器架構(gòu),本文提出的數(shù)據(jù)包解析器架構(gòu)硬件資源上有一定的消耗,但靈活性和吞吐率卻有了更高的提升,且增加了與處理器進(jìn)行交互的接口和中斷系統(tǒng)。傳統(tǒng)的并行多級流水架構(gòu),對于固定的以太網(wǎng)幀,解析速率可達(dá)100Gbps,但是靈活性較低。而靈活性最高的袋鼠系統(tǒng)架構(gòu),其四路并行解析核下的吞吐率為40Gbps,難以適應(yīng)更加高速的網(wǎng)絡(luò)。而本文提出的數(shù)據(jù)包解析器架構(gòu)能夠在工作頻率411MHz下達(dá)到105Gbps的解析速率,實(shí)現(xiàn)了數(shù)據(jù)包解析器的高靈活性和高吞吐率。
[Abstract]:With the rapid development of network technology in the past ten years, more and more devices have put forward an urgent need for the performance and configurability of routers and switches. In order to build efficient, stable and secure network systems, network equipment manufacturers pay more attention to the versatility and expansibility of their devices, which are reflected in the parsing of data packets, the identification of packet heads and the extraction of data. To support packet classification and security. In the past, the parsing of data packets was relatively simple, but with the addition of MPLS(Multi-Protocol Label switching and 802.1Q protocols, it became more and more difficult to parse packets at high speed. In the absence of a mezzanine protocol, the throughput of the packet resolver can reach 10-100 Gbps. However, in the interlayer protocol, the throughput of packet parser drops sharply. Therefore, in high-speed routers or switches, packet parsing becomes a potential bottleneck. In order to solve the above problem, we need to implement the solution more efficiently. This paper focuses on the architecture design of a flexible high-speed packet parser. Firstly, this paper studies and summarizes the architecture design methods of high-speed network packet parser in recent years, and compares and analyzes the advantages and disadvantages of various high-speed network packet parser architecture design. Secondly, a novel flexible packet parser architecture is proposed. By adopting the combined storage and query structure of the pipeline technology, including the CAM content Addressable memory and the LUT(Look up Table, this architecture can adapt to the new data packet header (including the mezzanine protocol and the tunneling Ethernet frame etc.). In addition, an off-line mapping algorithm is proposed. By off-line mapping, the architecture can resolve multiple protocols in a pipeline level at one time, and has high flexibility and throughput. Finally, this paper chooses the FPGA development platform of Altera Company and implements the architecture. According to the Ethernet frame in the actual network, the performance of the packet parser architecture is tested, and the information of hardware resources, working clock frequency and other information are given. Compared with the existing packet parser architecture, the hardware resources of the proposed packet parser architecture are consumed to a certain extent, but the flexibility and throughput are improved, and the interface and interrupt system are added to interact with the processor. Traditional parallel multilevel pipelining architecture, for fixed Ethernet frames, the resolution rate can be up to 100 GB pss, but the flexibility is low. However, the kangaroo system architecture with the highest flexibility has a throughput of 40Gbpsunder the four-channel parallel parsing kernel, so it is difficult to adapt to the higher speed network. The proposed packet parser architecture can achieve the 105Gbps resolution rate at the working frequency 411MHz, which can achieve the high flexibility and throughput of the packet parser.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN791

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