本文選題：高速低能耗 + 模數(shù)轉(zhuǎn)換器　； 參考：《電子科技大學(xué)》2017年碩士論文

【摘要】：為了適應(yīng)無線通信、可穿戴設(shè)備、高速數(shù)字信號(hào)處理等領(lǐng)域的高速發(fā)展,作為模擬信號(hào)與數(shù)字信號(hào)接口橋梁的模數(shù)轉(zhuǎn)換器(ADC)在高速、高精度、低能耗方向的研究將變得更加重要。由于高性能ADC在速度、精度、能耗之間相互限制,特別在工藝尺寸和電源電壓縮減的情況下,器件的小尺寸效應(yīng)更加突出,傳統(tǒng)模擬域的高速ADC架構(gòu)方案優(yōu)勢(shì)明顯降低。為了充分發(fā)揮先進(jìn)工藝線的優(yōu)勢(shì)及配合高速數(shù)字電路,本文在理論分析和建模驗(yàn)證的基礎(chǔ)上,基于標(biāo)準(zhǔn)40nm工藝設(shè)計(jì)實(shí)現(xiàn)了一款12位100MSps、應(yīng)用于超高速時(shí)間交織ADC中的單通道SAR ADC。首先,論文采用了非二進(jìn)制電容陣列架構(gòu)及較小的單位電容值,只需要將參考電平建立在冗余范圍內(nèi)即可,很大程度縮減了參考電平的建立時(shí)間,同時(shí)通過輔助DAC的補(bǔ)償作用,將DAC建立的參考電平理論值置于冗余區(qū)間的中間,使得ADC能夠同時(shí)容忍參考電平建立誤差的正向和負(fù)向偏差,另外使用較小的DAC電容值可以減小建立時(shí)的動(dòng)態(tài)功耗。其次,非二進(jìn)制電容陣列存在冗余量可以容忍量化出錯(cuò),ADC的高五位采用單級(jí)Latch鎖存比較器量化,低八位采用預(yù)放大+Latch進(jìn)行量化,兩種不同精度比較器分時(shí)工作,可有效降低高位量化的功耗開銷,在完成整個(gè)量化周期后將高精度比較器關(guān)閉,也可減小比較器的靜態(tài)功耗,單級(jí)Latch對(duì)高位量化時(shí),大信號(hào)輸入不經(jīng)過預(yù)放大級(jí)電路,減小比較器比較延時(shí)。最后,SAR邏輯電路采用新型鎖存型結(jié)構(gòu),配合異步時(shí)序邏輯的使用,數(shù)據(jù)鎖存及編碼延時(shí)相比于傳統(tǒng)的觸發(fā)器邏輯延時(shí)大大減小,同時(shí),本文還采用了比較器輸出結(jié)果不經(jīng)過鎖存直接編碼的技術(shù),有效的減小了SAR邏輯單元中數(shù)據(jù)鎖存的時(shí)間延時(shí)�；跇�(biāo)準(zhǔn)40nm工藝完成電路和版圖設(shè)計(jì)后,提取寄生參數(shù)并對(duì)電路進(jìn)行了整體性能驗(yàn)證仿真。在100MS/s采樣頻率,輸入信號(hào)接近奈奎斯特頻率附近時(shí),本次設(shè)計(jì)的SAR ADC的SFDR、SNDR、ENOB分別達(dá)到83.63d B、72.98dB、11.83bits,同時(shí)ADC的功耗開銷為6.1m W,FoM值為16.8fJ/conv,芯片CORE電路面積為0.018mm~2。最后該單通道ADC應(yīng)用于超高速時(shí)間交織ADC后在標(biāo)準(zhǔn)40nm CMOS工藝上進(jìn)行流片驗(yàn)證,測(cè)試結(jié)果顯示,DNL的最大最小值分別為1.08LSB和-0.864LSB;INL的最大最小值分別為3.76LSB和-0.48LSB,動(dòng)態(tài)范圍SFDR為:74.68dB,信噪失真比SNDR為:62.32dB,有效位數(shù)ENOB為:10.06Bit。
[Abstract]:In order to adapt to the rapid development of wireless communication, wearable devices, high-speed digital signal processing and other fields, ADCA / D converter, as an interface bridge between analog signal and digital signal, has high speed and high precision. Research on the direction of low energy consumption will become more important. Because high performance ADC is limited in speed, precision and energy consumption, especially in the case of process size and power supply voltage reduction, the small size effect of the device is more prominent, and the advantages of high-speed ADC architecture in traditional analog domain are obviously reduced. In order to give full play to the advantages of advanced process line and cooperate with high-speed digital circuit, based on theoretical analysis and modeling verification, a 12-bit 100MSps is implemented based on standard 40nm process design, which is applied to single-channel SAR ADC in ultra-high-speed time-interleaved ADC. First of all, the non-binary capacitor array architecture and small unit capacitance value are adopted in this paper. Only the reference level is set up in the redundant range, which greatly reduces the establishment time of the reference level. At the same time, the compensation function of DAC is assisted. The theoretical value of reference level established by DAC is placed in the middle of the redundant range, which enables ADC to tolerate both positive and negative deviation of reference level establishment error. In addition, the dynamic power consumption can be reduced by using smaller value of DAC capacitance. Secondly, the redundancy of non-binary capacitor array can tolerate quantization error. The high five bits are quantized by single stage Latch latch comparator, and the low eight bits are quantized by preamplifying Latch. The two kinds of comparators with different precision work in time sharing. It can effectively reduce the power cost of high quantization, turn off the high precision comparator after the whole quantization cycle, but also reduce the static power consumption of the comparator. When single stage Latch quantizes the high position, the large signal input does not go through the preamplifier stage circuit. Reduce comparator comparison delay. Finally, the SAR logic circuit adopts a new latch structure, and with the use of asynchronous sequential logic, the data latch and coding delay are greatly reduced compared with the traditional trigger logic delay, at the same time, This paper also adopts the technology that the output result of comparator is not directly encoded by latch, which effectively reduces the time delay of data latch in SAR logic unit. After circuit and layout design is completed based on standard 40nm process, parasitic parameters are extracted and the overall performance of the circuit is verified and simulated. When the sampling frequency of 100MS/s and the input signal are close to Nyquist frequency, the SNDRENOB of SAR ADC designed in this paper reaches 83.63dBU 72.98dBU 11.83 bits, meanwhile, the power consumption of ADC is 6.1m WN FoM is 16.8fJ / conv. and the area of chip CORE circuit is 0.018mm / m ~ (-2). Finally, the single-channel ADC is used to verify the flow sheet in the standard 40nm CMOS process after interleaving ADC at ultra-high speed. The results show that the maximum and minimum values of 1.08LSB and -0.864 LSB-INL are 3.76LSB and -0.48LSB. the dynamic range SFDR is 74.68dB, the signal-noise-distortion ratio (SNDR) is: 62.32dB, and the effective digit ENOB is 10.0: Bit06.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN792

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本文編號(hào)：1945235