本文選題：逐次逼近型模數(shù)轉(zhuǎn)換器 + 高速低功耗�。� 參考：《東南大學(xué)》2017年碩士論文

【摘要】：在表面肌電信號處理電路中大都需要模數(shù)轉(zhuǎn)換器來將肌電信號這個模擬信號轉(zhuǎn)換為數(shù)字信號,而應(yīng)用的特殊領(lǐng)域需要模數(shù)轉(zhuǎn)換器必須具有中等速度、中等精度和低功耗的特點,并且在CMOS工藝下較好實現(xiàn)。而逐次逼近型模數(shù)轉(zhuǎn)換器(Successive Approximation Register Analog-to-Digital Converter,SAR ADC)具有由于具有中等的精度和中等的速度,采用CMOS工藝實現(xiàn)可保證較小的面積和功耗,在精度、速度、功耗和成本方面有著綜合優(yōu)勢,因而被廣泛的應(yīng)用于醫(yī)療、無線傳感網(wǎng)、數(shù)據(jù)存儲等領(lǐng)域。本課題結(jié)合生物醫(yī)療應(yīng)用領(lǐng)域的的要求,采用TSMC0.18μm CMOS工藝,設(shè)計了一款12bit 60MS/s低功耗SAR ADC。論文分別從構(gòu)成SAR ADC的三個主要模塊進行研究并改進SAR ADC。采用柵壓自舉開關(guān)、分段電容和單調(diào)開關(guān)切換方法提高DAC的線性度,減小電容的面積,降低功耗,采用局部共質(zhì)心的版圖布局提高匹配性;改進雙尾電流動態(tài)比較器,提高電路的穩(wěn)定性,降低了比較器的延時,降低了功耗和回踢噪聲,對比較器進行了校準(zhǔn),將低失調(diào)電壓。在邏輯控制上中使用到的D型觸發(fā)器,選擇真單向時鐘(True Single Phase Clock,TSPC)的D型觸發(fā)器,并進行改進,增加復(fù)位端口,簡化了電路結(jié)構(gòu),降低電路動態(tài)功耗,提高電路的速度。本設(shè)計在Cadence環(huán)境下,對SAR ADC中關(guān)鍵模塊和整體電路進行了電路前仿真和版圖后仿真。版圖總面積為550μm*175μm,電路后仿真的結(jié)果是:采樣率為60MS/s時,SARADC的信號噪聲失真比達到69dB,無雜散動態(tài)范圍為67.4dB,有效位達到10.9bit,電路總功耗到達9.36mW,滿足設(shè)計指標(biāo)要求。
[Abstract]:In the surface EMG signal processing circuit, the analog-to-digital converter is required to convert the analog signal into digital signal, and the application of the special field requires that the ADC must have the characteristics of medium speed, medium accuracy and low power consumption. And it is well realized in CMOS process. The successive approximation analog-to-digital converter (ADC) has the advantages of low area and power consumption due to its moderate accuracy and medium speed, and has the advantages of precision, speed, power consumption and cost. Therefore, it is widely used in medical treatment, wireless sensor network, data storage and other fields. According to the requirements of biomedical application field, a low power 12bit 60MS/s SAR CMOS is designed by using TSMC0.18 渭 m CMOS process. In this paper, three main modules of SAR ADC are studied and improved. Using the gate voltage bootstrap switch, piecewise capacitance and monotone switch switching method to improve the linearity of DAC, reduce the area of capacitance, reduce power consumption, use the layout of local cocenter to improve matching, improve the dynamic comparator of double tail current, The stability of the circuit is improved, the delay of the comparator is reduced, the power consumption and backkick noise are reduced, and the comparator is calibrated to reduce the offset voltage. The D type flip-flop used in logic control, the true unidirectional clock true Single Phase lockTSPC type D flip-flop is selected and improved to increase the reset port, simplify the circuit structure, reduce the dynamic power consumption of the circuit and improve the speed of the circuit. In the Cadence environment, the key modules and the whole circuit in SAR ADC are simulated before and after layout. The total layout area is 550 渭 m ~ (175) 渭 m. The simulation results are as follows: when the sampling rate is 60MS/s, the signal noise distortion ratio is 69 dB, the non-spurious dynamic range is 67.4 dB, the effective bit is 10.9 bit, and the total power consumption of the circuit is 9.36 MW, which meets the design requirements.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN792

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