本文選題：時(shí)鐘數(shù)據(jù)恢復(fù) + 高速串行接口��； 參考：《國防科學(xué)技術(shù)大學(xué)》2015年碩士論文

【摘要】：隨著集成電路行業(yè)的迅速發(fā)展,以及信息流量需求的不斷增大,目前高性能芯片的數(shù)據(jù)計(jì)算和處理速度已經(jīng)很快,而芯片之間的數(shù)據(jù)傳輸速率相對(duì)落后成為了制約芯片性能的最大瓶頸。傳統(tǒng)的并行傳輸技術(shù)因其需要過多的管腳數(shù)目、各數(shù)據(jù)位之間的傳輸延時(shí)不匹配和需要同步時(shí)鐘等原因而逐漸被淘汰,取而代之的是原本應(yīng)用于光纖通信的串行傳輸技術(shù)——SerDes(Serializer/Deserializer)。時(shí)鐘數(shù)據(jù)恢復(fù)(CDR)電路是整個(gè)Ser Des系統(tǒng)的核心,也是制約著其性能的關(guān)鍵所在,它的主要功能是從接收到的含有較大串?dāng)_和抖動(dòng)的數(shù)據(jù)中恢復(fù)出時(shí)鐘,并利用這個(gè)時(shí)鐘對(duì)該數(shù)據(jù)進(jìn)行采樣,從而得到正確的數(shù)據(jù)。本文基于65 nm CMOS工藝,完成了對(duì)高速SerDes中的關(guān)鍵模塊CDR的研究和設(shè)計(jì)。本文首先從MATLAB建模出發(fā),運(yùn)用數(shù)學(xué)模型深入研究了CDR的工作原理,然后在模型的指導(dǎo)下,完成了相應(yīng)的電路設(shè)計(jì)和版圖設(shè)計(jì)。本文設(shè)計(jì)的CDR采用基于相位插值(PI)的雙環(huán)結(jié)構(gòu)實(shí)現(xiàn),其中一個(gè)環(huán)路為鎖相環(huán)(PLL),另一個(gè)環(huán)路為延遲鎖相環(huán)(DLL)。其中DLL由相位插值電路、高速采樣電路、數(shù)據(jù)分接電路、邊沿檢測(cè)電路和二階數(shù)字環(huán)路濾波器等組成。支持1.25 Gb/s~6.25 Gb/s的寬范圍工作速率,支持半速、全速和倍速三種工作模式,降低了鎖相環(huán)的設(shè)計(jì)難度,且具有帶寬可調(diào)和一定頻差容忍等特點(diǎn),其中相位插值電路采用7 bit的結(jié)構(gòu)。為了提高有頻差時(shí)的鎖定速度,本文還創(chuàng)新性地在二階數(shù)字環(huán)路濾波器中增加了快速鎖定算法,使其在頻差為1000 ppm時(shí)鎖定速度可以提高一倍,能夠滿足突發(fā)性數(shù)據(jù)傳輸?shù)囊�。仿真結(jié)果表明,在工作速率為6.25 Gb/s時(shí),該CDR抖動(dòng)傳輸帶寬為2 MHz~7.5 MHz可調(diào),最大頻差容忍為±1800 ppm,在頻差為1800 ppm時(shí)恢復(fù)出的數(shù)據(jù)眼圖寬度大于0.89 UI,功耗小于16.4 mW。其中相位插值電路的DNL為2.8o,INL為7.2o。仿真結(jié)果滿足系統(tǒng)設(shè)計(jì)指標(biāo)。
[Abstract]:With the rapid development of integrated circuit industry and the increasing demand of information flow, the data calculation and processing speed of high performance chip has been very fast. The relative lag of data transmission rate between chips has become the biggest bottleneck of chip performance. The traditional parallel transmission technology is gradually eliminated because of the excessive number of pins, the mismatch of transmission delay between different data bits and the need of synchronous clock. Instead, SerDesSerializer / Deserializerer, the serial transmission technology originally used in optical fiber communication, is replaced. The clock data recovery circuit is the core of the whole Ser Des system and the key to its performance. Its main function is to recover the clock from the received data with large crosstalk and jitter. This clock is used to sample the data to get the correct data. Based on 65 nm CMOS process, the research and design of CDR, a key module in high speed SerDes, is completed in this paper. Based on the MATLAB modeling, the working principle of CDR is studied deeply by using the mathematical model, and then the corresponding circuit design and layout design are completed under the guidance of the model. The CDR designed in this paper is based on phase interpolation (Pi) double loop structure. One loop is phase locked loop (PLL) and the other is delay phase locked loop (DLL). DLL consists of phase interpolation circuit, high speed sampling circuit, data demultiplexing circuit, edge detection circuit and second order digital loop filter. It supports three working modes of half speed, full speed and double speed, which reduces the design difficulty of phase-locked loop, and has the characteristics that bandwidth can be reconciled with a certain frequency difference tolerance. Among them, the phase interpolation circuit adopts a 7 bit structure. In order to improve the locking speed with frequency difference, this paper also creatively adds a fast locking algorithm to the second-order digital loop filter, which can double the locking speed when the frequency difference is 1000 ppm, and can meet the requirements of sudden data transmission. The simulation results show that when the operating rate is 6.25 Gb/s, the CDR jitter transmission bandwidth is 2 MHz~7.5 MHz adjustable, the maximum frequency difference tolerance is 鹵1800 ppm, and the recovery data eye width is greater than 0.89 UIwhen the frequency difference is 1800 ppm, and the power consumption is less than 16.4 MW. The DNL of the phase interpolation circuit is 2.8oNL and 7.2o. The simulation results meet the system design criteria.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN432

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