本文選題：三維片上網(wǎng)絡(luò) + 映射算法�。� 參考：《西安電子科技大學(xué)》2015年碩士論文

【摘要】：隨著嵌入式領(lǐng)域的快速發(fā)展,片上系統(tǒng)瓶頸問題日益明顯,相關(guān)的研究人員提出了將計算機(jī)網(wǎng)絡(luò)的理念引入嵌入式系統(tǒng)設(shè)計領(lǐng)域,因此片上網(wǎng)絡(luò)應(yīng)運(yùn)而生。片上網(wǎng)絡(luò)將通信節(jié)點(diǎn)和資源節(jié)點(diǎn)分離,以分組交換為基本通訊技術(shù),采用全局異步-局部同步的通訊機(jī)制,憑借路由策略和交換技術(shù)在功耗和延時方面表現(xiàn)出更優(yōu)越的性能,從而滿足嵌入式發(fā)展的需求,成為了如今嵌入式系統(tǒng)設(shè)計的大方向。片上網(wǎng)絡(luò)想要發(fā)揮功耗和延時方面的優(yōu)越性需要一個合理高效的映射算法。三維片上網(wǎng)絡(luò)的映射算法是一個NP完全問題,有許多智能算法被應(yīng)用于片上網(wǎng)絡(luò)的映射問題上,但是仍然存在算法效率低,映射不合理以及功耗和延時不能兼顧的問題,因此我們還需要對三維片上網(wǎng)絡(luò)的映射策略進(jìn)行進(jìn)一步研究。本文主要針對三維片上網(wǎng)絡(luò)的映射算法做了相關(guān)研究。首先簡要介紹了三維片上網(wǎng)絡(luò)的拓?fù)浣Y(jié)構(gòu)、片上網(wǎng)絡(luò)平臺、路由算法、映射相關(guān)理論以及功耗和延時模型,進(jìn)而分別對基于遺傳、蟻群和粒子群的映射算法進(jìn)行了實現(xiàn)和性能分析,鑒于遺傳算法、蟻群算法和粒子群算法的不足之處,本文設(shè)計和實現(xiàn)了一種基于混沌粒子群的映射算法,算法主要分為兩個個階段,前一階段依據(jù)DAG圖所提供的信息得到各個任務(wù)的優(yōu)先權(quán)值,關(guān)鍵路徑上任務(wù)的優(yōu)先權(quán)值最大,優(yōu)先映射前驅(qū)任務(wù)已經(jīng)完成的關(guān)鍵路徑任務(wù)來縮短任務(wù)執(zhí)行總時間;第二階段利用第一階段生成的任務(wù)到內(nèi)核的映射結(jié)果,借助混沌粒子群算法和功耗延時模型來生成近似最優(yōu)的內(nèi)核映射方案。通過TGFF(隨機(jī)任務(wù)生成器)生成隨機(jī)任務(wù)集合,設(shè)置相關(guān)的算法參數(shù),運(yùn)用Java開發(fā)軟件Eclipse分別借助遺傳算法、蟻群算法和混沌粒子群算法來編寫映射算法。按照編寫的映射算法將任務(wù)數(shù)據(jù)先向內(nèi)核映射,再將內(nèi)核向網(wǎng)絡(luò)節(jié)點(diǎn)映射來完成仿真;仿真結(jié)果表明:相比于遺傳算法和蟻群算法,基于混沌粒子群的映射算法在功耗、延時整體性能以及收斂效果方面都比較好。論文完成了三維片上網(wǎng)絡(luò)映射算法設(shè)計及仿真驗證。論文工作對三維片上網(wǎng)絡(luò)映射算法的研究有一定的參考意義。
[Abstract]:With the rapid development of embedded field, the bottleneck problem of on-chip system becomes more and more obvious. Related researchers put forward the idea of introducing the concept of computer network into the field of embedded system design, so the on-chip network came into being. The on-chip network separates the communication node from the resource node, takes packet switching as the basic communication technology, adopts the global asynchronous local synchronous communication mechanism, and shows better performance in power consumption and delay by means of routing strategy and switching technology. Therefore, to meet the needs of embedded development has become the main direction of embedded system design. In order to exert the advantages of power consumption and delay, the on-chip network needs a reasonable and efficient mapping algorithm. The mapping algorithm of 3D on-chip network is a NP-complete problem. Many intelligent algorithms have been applied to the mapping problem of the on-chip network. However, there are still some problems such as low efficiency, unreasonable mapping, and the imbalance of power consumption and delay. Therefore, we need to further study the mapping strategy of three-dimensional on-chip network. This paper mainly focuses on the mapping algorithm of three-dimensional on-chip network. Firstly, the topology of 3D on-chip network, on-chip network platform, routing algorithm, mapping theory, power consumption and delay model are briefly introduced. The mapping algorithm of ant colony and particle swarm is implemented and its performance is analyzed. In view of the deficiency of genetic algorithm, ant colony algorithm and particle swarm optimization algorithm, a mapping algorithm based on chaotic particle swarm optimization is designed and implemented in this paper. The algorithm is mainly divided into two stages. In the previous stage, the priority value of each task is obtained according to the information provided by the DAG diagram, and the priority value of the task on the critical path is the largest. First mapping the critical path tasks completed by the precursor task to shorten the total task execution time; the second stage uses the mapping results from the first phase to the kernel. Chaotic particle swarm optimization algorithm and power delay model are used to generate an approximate optimal kernel mapping scheme. The random task set is generated by TGFF (random task generator), and the related algorithm parameters are set up. The mapping algorithm is compiled by Java development software Eclipse with the help of genetic algorithm, ant colony algorithm and chaotic particle swarm optimization algorithm, respectively. According to the mapping algorithm, the task data is mapped to the kernel first and then the kernel to the network node to complete the simulation. The simulation results show that compared with genetic algorithm and ant colony algorithm, the mapping algorithm based on chaotic particle swarm in power consumption. The overall performance of delay and convergence effect are better. The algorithm design and simulation verification of three-dimensional on-chip network mapping are completed in this paper. The work of this paper has some reference significance for the research of three-dimensional on-chip network mapping algorithm.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN47;TP18

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本文編號：1937049