本文選題：FPGA + NBTI效應(yīng)��； 參考：《哈爾濱工業(yè)大學(xué)》2017年碩士論文

【摘要】：FPGA(Field Programmable Gate Array)現(xiàn)場(chǎng)可編輯邏輯門陣列,是當(dāng)今硬件設(shè)計(jì)中應(yīng)用十分廣泛的新型高性能邏輯器件。FPGA具有功能強(qiáng)大、開發(fā)周期短、可反復(fù)編程修改、開發(fā)工具智能化等優(yōu)點(diǎn)。但是隨著超大規(guī)模集成電路加工工藝的提升日益困難,FPGA性能已經(jīng)逐漸達(dá)到其物理極限。同時(shí),FPGA器件面臨的可靠性問題也日益嚴(yán)重。在眾多可靠性問題中,負(fù)偏壓溫度不穩(wěn)定性效應(yīng)(Negative Bias Temperature Instability,NBTI)是FPGA器件失效的首要原因,NBTI效應(yīng)造成的性能退化使FPGA隨著時(shí)間推移產(chǎn)生更多的信號(hào)延遲從而導(dǎo)致信號(hào)在邏輯門之間的傳輸時(shí)間逐漸延長(zhǎng),并最終導(dǎo)致電路出現(xiàn)時(shí)序違規(guī)問題。本文首先分析了FPGA內(nèi)部結(jié)構(gòu),以及NBTI效應(yīng)造成FPGA工作速率退化的本質(zhì)原因。以此為基礎(chǔ),本文設(shè)計(jì)了FPGA器件加速退化試驗(yàn)平臺(tái),利用基于失效物理的方法,對(duì)FPGA進(jìn)行加速退化試驗(yàn),獲取FPGA在不同應(yīng)力組合情況下的退化情況。本文隨后研究了電源電壓對(duì)FPGA路徑延遲的影響,并利用HSPICE軟件仿真分析了電源電壓對(duì)FPGA內(nèi)部查找表單元結(jié)構(gòu)和互連結(jié)構(gòu)延遲時(shí)間的影響。此外,本文還提出基于環(huán)形振蕩器的路徑延遲測(cè)量方法,通過(guò)在FPGA中進(jìn)行真實(shí)硬件實(shí)驗(yàn)驗(yàn)證了電源電壓升高對(duì)于路徑延遲退化的抑制作用。以此研究為基礎(chǔ),本文提出了基于自適應(yīng)電源調(diào)整的FPGA抗退化方法基本框架,并設(shè)計(jì)退化傳感器對(duì)FPGA路徑延遲退化情況進(jìn)行實(shí)時(shí)監(jiān)測(cè),同時(shí)根據(jù)退化情況對(duì)電源電壓進(jìn)行動(dòng)態(tài)調(diào)整,已達(dá)到保證電路工作性能,并且減小電路功率消耗的目的。最后,本文搭建了基于自適應(yīng)電源調(diào)整方法完整的實(shí)現(xiàn)平臺(tái)和驗(yàn)證平臺(tái)。通過(guò)該平臺(tái)證明了該方法可以有效消除FPGA退化的影響,具有魯棒性強(qiáng)、響應(yīng)速度快的特點(diǎn)。并且以FFT運(yùn)算核作為試驗(yàn)對(duì)象,將該方法與傳統(tǒng)方法保留時(shí)序余量法進(jìn)行了功耗和性能對(duì)比。在工作頻率相同的情況下,該方法最大可將功耗降低57.98%,在功耗相同的情況下,該方法最高可將電路最大工作頻率提高14.78%。
[Abstract]:FPGA(Field Programmable Gate Array) field editable logic gate array is a new type of high performance logic device which is widely used in hardware design nowadays. It has many advantages such as powerful function, short development period, reprogramming modification, intelligent development tool and so on. However, with the improvement of VLSI processing technology, FPGA performance has gradually reached its physical limit. At the same time, the reliability of FPGA devices is becoming more and more serious. Among the many reliability problems, The negative bias temperature instability effect (NBTI) is the primary reason for the failure of FPGA devices. The performance degradation caused by the NBTI effect causes the FPGA to produce more signal delays over time, which leads to the gradual extension of signal transmission time between logic gates. And eventually lead to circuit timing violations. In this paper, we first analyze the internal structure of FPGA and the essential cause of the degradation of FPGA working rate caused by NBTI effect. Based on this, an accelerated degradation test platform for FPGA devices is designed. Using the method of failure physics, the accelerated degradation test of FPGA is carried out, and the degradation of FPGA under different stress combinations is obtained. Then, the influence of power supply voltage on FPGA path delay is studied, and the influence of power supply voltage on FPGA internal lookup form element structure and interconnect structure delay time is simulated by HSPICE software. In addition, a path delay measurement method based on ring oscillator is proposed. The effect of voltage rise on path delay degradation is verified by a real hardware experiment in FPGA. On the basis of this research, this paper presents the basic framework of FPGA anti-degradation method based on adaptive power supply adjustment, and designs a degradation sensor to monitor the degradation of FPGA path delay in real time. At the same time, the power supply voltage is dynamically adjusted according to the degradation situation, which can ensure the circuit performance and reduce the power consumption of the circuit. Finally, a complete implementation platform and verification platform based on adaptive power adjustment method are built. It is proved by the platform that this method can effectively eliminate the influence of FPGA degradation and has the characteristics of strong robustness and fast response speed. Taking the FFT operation kernel as the experimental object, the power consumption and performance of the proposed method are compared with that of the traditional method. In the case of the same operating frequency, the maximum power consumption can be reduced by 57.98. In the case of the same power consumption, the maximum operating frequency of the circuit can be increased by 14.78.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN791

【參考文獻(xiàn)】

相關(guān)期刊論文 前6條

1 黃俊英;林郁;張超;楊海鋼;;基于垂直擴(kuò)散的FPGA溫度優(yōu)化布局算法[J];計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào);2017年01期

2 薛士然;;16nm FinFET+技術(shù)帶來(lái)FPGA的巨大變革[J];單片機(jī)與嵌入式系統(tǒng)應(yīng)用;2015年04期

3 宋奮韜;王夢(mèng)瑩;付志遠(yuǎn);;FPGA發(fā)展概論[J];科技信息;2012年23期

4 靳松;韓銀和;李華偉;李曉維;;考慮工作負(fù)載影響的電路老化預(yù)測(cè)方法[J];計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào);2010年12期

5 黃勇;恩云飛;章曉文;;NBTI效應(yīng)的退化表征[J];半導(dǎo)體技術(shù);2007年07期

6 簡(jiǎn)貴胄,葛寧,馮重熙;靜態(tài)時(shí)序分析方法的基本原理和應(yīng)用[J];計(jì)算機(jī)工程與應(yīng)用;2002年14期

相關(guān)博士學(xué)位論文 前2條

1 徐輝;集成電路老化預(yù)測(cè)與容忍[D];合肥工業(yè)大學(xué);2013年

2 李康;超深亞微米集成電路可靠性設(shè)計(jì)與建模方法[D];西安電子科技大學(xué);2005年

相關(guān)碩士學(xué)位論文 前4條

1 張誠(chéng)成;基于線性規(guī)劃的集成電路低功耗設(shè)計(jì)和抗退化方法研究[D];哈爾濱工業(yè)大學(xué);2016年

2 花修春;基本單元電路的NBTI機(jī)制下性能退化分析及改進(jìn)方法研究[D];華東師范大學(xué);2016年

3 王超;VLSI老化預(yù)測(cè)與抗老化技術(shù)研究[D];合肥工業(yè)大學(xué);2013年

4 孟祥志;FPGA的靜態(tài)時(shí)序分析研究與設(shè)計(jì)[D];復(fù)旦大學(xué);2012年

，

本文編號(hào)：1915898