基于FPGA的視頻實(shí)時(shí)采集系統(tǒng)關(guān)鍵技術(shù)研究
本文選題:FPGA + 視頻。 參考:《北方民族大學(xué)》2017年碩士論文
【摘要】:隨著科技的進(jìn)步和社會的發(fā)展,視頻實(shí)時(shí)采集系統(tǒng)得到了越來越多的應(yīng)用。由于FPGA具有大容量的邏輯資源和極強(qiáng)的并行處理能力,因而FPGA特別適合作為視頻實(shí)時(shí)采集系統(tǒng)的核心處理單元。而且得益于FPGA芯片具有可重復(fù)編程性,這就使得基于FPGA的視頻實(shí)時(shí)采集系統(tǒng)相對于其它類型的視頻實(shí)時(shí)采集系統(tǒng)來說,系統(tǒng)的維護(hù)和升級變得更為簡單。當(dāng)系統(tǒng)硬件需要少量改進(jìn)時(shí),可以在FPGA內(nèi)部設(shè)計(jì)新的片內(nèi)邏輯,而不用重新進(jìn)行FPGA芯片外圍電路的設(shè)計(jì),這就在一定程度上節(jié)約了資源,減少了人力物力的損耗。本文主要對基于FPGA的視頻實(shí)時(shí)采集系統(tǒng)進(jìn)行了深入研究,將整個(gè)系統(tǒng)按照相應(yīng)功能劃分成五個(gè)模塊,并將系統(tǒng)涉及的一些關(guān)鍵技術(shù)穿插在相應(yīng)模塊中進(jìn)行設(shè)計(jì)。全局時(shí)鐘模塊,為系統(tǒng)的其他模塊提供所需的時(shí)鐘。攝像頭配置模塊,通過串行相機(jī)控制總線接口完成對OV7725 CMOS Sensor內(nèi)部寄存器的配置,使得圖像傳感器能夠輸出預(yù)期配置的視頻數(shù)據(jù)。攝像頭視頻流采集模塊,用于實(shí)時(shí)采集攝像頭產(chǎn)生的視頻信號,并對采集到的視頻信號進(jìn)行同步化設(shè)計(jì),最后通過采樣和拼接,輸出處理后的行場信號。SDRAM存儲控制模塊,通過對SDRAM存儲器的控制,實(shí)現(xiàn)大容量視頻圖像數(shù)據(jù)的緩存,以及跨時(shí)鐘域數(shù)據(jù)的交互。VGA顯示控制模塊,用于產(chǎn)生VGA顯示器正常工作時(shí)需要的時(shí)序信號,實(shí)現(xiàn)實(shí)時(shí)視頻圖像的VGA顯示驅(qū)動(dòng)功能。系統(tǒng)的開發(fā)環(huán)境采用Quartus II 13.0,使用Verilog HDL語言完成對系統(tǒng)各模塊的編寫。通過Quartus II自帶的仿真工具對系統(tǒng)的一些功能模塊進(jìn)行了仿真。系統(tǒng)的全局時(shí)鐘模塊,是通過Altera公司的FPGA中內(nèi)嵌的鎖相環(huán)進(jìn)行設(shè)計(jì)的,通過Quartus II軟件可以很方便地對鎖相環(huán)進(jìn)行設(shè)置,能夠有效縮短開發(fā)時(shí)間。在SDRAM存儲控制模塊中使用了DCFIFO,解決了跨時(shí)鐘域數(shù)據(jù)的交互問題。實(shí)驗(yàn)結(jié)果表明,系統(tǒng)能夠正常工作,且采集到的視頻畫面比較清晰,能夠?qū)崿F(xiàn)視頻實(shí)時(shí)采集的既定目標(biāo),具有一定的科研和應(yīng)用價(jià)值。
[Abstract]:With the progress of science and technology and the development of society, video real-time acquisition system has been applied more and more. Because FPGA has large capacity of logic resources and strong parallel processing ability, FPGA is especially suitable as the core processing unit of video real-time acquisition system. Because of the repeatability of FPGA chip, the maintenance and upgrade of real-time video capture system based on FPGA is much simpler than that of other kinds of real-time video acquisition system. When the hardware of the system needs a little improvement, the new in-chip logic can be designed in FPGA, without redesigning the peripheral circuit of the FPGA chip, which saves the resources and reduces the loss of manpower and material resources to a certain extent. In this paper, the video real-time acquisition system based on FPGA is deeply studied, the whole system is divided into five modules according to the corresponding functions, and some key technologies involved in the system are interleaved in the corresponding modules to design. The global clock module provides the required clock for other modules of the system. The camera configuration module, through the serial camera control bus interface to complete the configuration of the OV7725 CMOS Sensor internal register, so that the image sensor can output the desired configuration of video data. The video stream acquisition module of the camera is used to collect the video signal generated by the camera in real time, and the synchronization design of the collected video signal is carried out. Finally, through sampling and splicing, the processed row field signal. SDRAM storage control module is output. Through the control of SDRAM memory, the cache of large capacity video image data is realized, and the interactive. VGA display control module of cross-clock domain data is used to generate the timing signals needed by the VGA display when it is working normally. Realize the real-time video image VGA display driver function. The development environment of the system is Quartus II 13.0, and Verilog HDL language is used to complete the writing of each module of the system. Some functional modules of the system are simulated by Quartus II simulation tools. The global clock module of the system is designed by the phase-locked loop embedded in the FPGA of Altera Company. The Quartus II software can set the PLL conveniently and shorten the development time effectively. DCFIFO is used in SDRAM storage control module to solve the problem of data interaction across clock domain. The experimental results show that the system can work normally, and the captured video picture is clear, and it can realize the fixed goal of real-time video acquisition, which has certain scientific research and application value.
【學(xué)位授予單位】:北方民族大學(xué)
【學(xué)位級別】:碩士
【學(xué)位授予年份】:2017
【分類號】:TN791;TN948.6
【參考文獻(xiàn)】
相關(guān)期刊論文 前10條
1 劉禎;;視頻監(jiān)控系統(tǒng)發(fā)展的分析與研究[J];科技創(chuàng)新與應(yīng)用;2017年01期
2 王星文;張延巍;;視頻監(jiān)控系統(tǒng)在醫(yī)院安全管理中的作用[J];科技與創(chuàng)新;2016年24期
3 胡元君;;工業(yè)4.0模式下電子元器件SMT產(chǎn)品質(zhì)量提升策略[J];江蘇科技信息;2016年32期
4 林倩;;I2C協(xié)議解析及實(shí)測波形[J];數(shù)字技術(shù)與應(yīng)用;2016年11期
5 羅瀟磊;孫德新;;CMOS圖像傳感器的多斜率積分線性恢復(fù)方法[J];半導(dǎo)體光電;2016年03期
6 陸辰鴻;胡越黎;周俊;;基于訓(xùn)練方式的存儲器時(shí)鐘信號的自適應(yīng)同步[J];上海大學(xué)學(xué)報(bào)(自然科學(xué)版);2015年04期
7 楊會建;楊陽;張環(huán);朱瑩;;基于SCCB總線配置的FPGA視頻采集系統(tǒng)設(shè)計(jì)[J];長春理工大學(xué)學(xué)報(bào)(自然科學(xué)版);2015年04期
8 杜宗展;王振河;馮迎春;;基于FPGA的VGA圖像顯示系統(tǒng)的設(shè)計(jì)[J];現(xiàn)代電子技術(shù);2015年16期
9 張?zhí)煳?劉文怡;;基于LVDS和PCI接口的高速圖像傳輸系統(tǒng)設(shè)計(jì)[J];電子技術(shù)應(yīng)用;2014年07期
10 吳維起;劉安芝;高廣珠;;FPGA設(shè)計(jì)中功耗的分析與仿真[J];現(xiàn)代電子技術(shù);2014年05期
相關(guān)碩士學(xué)位論文 前10條
1 馬牙川;基于FPGA的智能工業(yè)相機(jī)系統(tǒng)的研究[D];浙江大學(xué);2016年
2 魏艷艷;方向互補(bǔ)的數(shù)字圖像脈沖噪聲去除算法研究[D];蘭州大學(xué);2015年
3 吳華宇;基于監(jiān)控視頻的高校教室占用率統(tǒng)計(jì)系統(tǒng)[D];沈陽工業(yè)大學(xué);2015年
4 魏曉輝;基于FPGA的實(shí)時(shí)視頻圖像采集與VGA顯示系統(tǒng)設(shè)計(jì)研究[D];西安電子科技大學(xué);2015年
5 劉文龍;基于FPGA的視頻采集系統(tǒng)設(shè)計(jì)[D];青島科技大學(xué);2014年
6 李建華;基于FPGA的視頻采集系統(tǒng)設(shè)計(jì)[D];長安大學(xué);2014年
7 程換麗;視頻監(jiān)控中遺留物體的檢測研究[D];河北科技大學(xué);2014年
8 李斌來;視頻監(jiān)控系統(tǒng)傳輸技術(shù)的研究與實(shí)現(xiàn)[D];吉林大學(xué);2013年
9 王巖;視頻信號采集與網(wǎng)絡(luò)傳輸系統(tǒng)的研究與實(shí)現(xiàn)[D];大連海事大學(xué);2011年
10 胡飛虎;基于計(jì)算機(jī)視覺的財(cái)產(chǎn)保護(hù)系統(tǒng)[D];浙江工業(yè)大學(xué);2011年
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