本文選題：單粒子效應(yīng) + 多位翻轉(zhuǎn)��； 參考：《深圳大學(xué)》2017年碩士論文

【摘要】：隨著集成電路朝著更小的工藝尺寸,更高及集成度發(fā)展時(shí),輻射環(huán)境中的粒子入射的影響越來越嚴(yán)重。因?yàn)榱Ｗ尤肷湓斐傻膯瘟Ｗ有?yīng)已經(jīng)成為航空航天電路失效的最重要原因之一。工藝尺寸的縮減使得節(jié)點(diǎn)之間的間距減小,導(dǎo)致在單粒子轟擊發(fā)生時(shí),節(jié)點(diǎn)之間的電荷共享越來越明顯,由此引發(fā)的多位翻轉(zhuǎn)使得一些傳統(tǒng)的抗輻射設(shè)計(jì)如加大器件之間的間距,保護(hù)環(huán)等防護(hù)方法失效�；陔姾晒蚕砗投辔环D(zhuǎn)的基礎(chǔ)上提出的脈沖窄化效應(yīng),是一種新型的防輻射設(shè)計(jì)思路。本文基于90納米和65納米CMOS雙阱工藝,研究了90納米工藝下基于脈沖窄化的抗輻射版圖設(shè)計(jì)方法,65納米工藝下基礎(chǔ)邏輯電路的版圖設(shè)計(jì)方法,65納米工藝下復(fù)合邏輯電路的版圖設(shè)計(jì)方法,65納米工藝下抗輻射電路版圖設(shè)計(jì)方法。以此總結(jié)出脈沖窄化在版圖設(shè)計(jì)中的應(yīng)用條件與準(zhǔn)則。主要內(nèi)容如下:(1)通過TCAD軟件進(jìn)行90納米工藝和65納米工藝的三維器件建模仿真。在90納米工藝下,通過設(shè)置不同的器件間距和不同的入射粒子LET值的實(shí)驗(yàn)。解釋在大的器件間距或者小的入射粒子LET值的情況下,輸出節(jié)點(diǎn)出現(xiàn)的雙峰電壓現(xiàn)象。基于脈沖窄化的工作原理,提出或門PMOS版圖部分適用脈沖窄化的冗余器件設(shè)計(jì)方法,與門的NMOS版圖部分適用冗余設(shè)計(jì)方法,提出最小間距設(shè)計(jì)方法和高LET值器件不敏感的觀點(diǎn)。(2)對比或門PMOS部分在90納米和65納米的粒子入射實(shí)驗(yàn)結(jié)果。提出隨著器件工藝尺寸的縮減,或門的PMOS部分使用傳統(tǒng)版圖即可抵御單粒子脈沖無需冗余設(shè)計(jì)。對比與門NMOS部分在90納米和65納米的粒子入射實(shí)驗(yàn)結(jié)果,提出隨著器件工藝尺寸的縮減,與門的NMOS部分使用冗余設(shè)計(jì)的效果會(huì)越來越好。(3)在65納米工藝,進(jìn)行復(fù)合邏輯電路的三維模型仿真實(shí)驗(yàn)。對比邏輯等效電路替換和復(fù)合邏輯電路的冗余設(shè)計(jì)兩種方法,證明冗余設(shè)計(jì)方法在設(shè)計(jì)的簡易度和穩(wěn)定性上更為優(yōu)秀。應(yīng)用脈沖窄化的設(shè)計(jì)方法的建議:1.復(fù)雜的邏輯電路表達(dá)式應(yīng)該通過邏輯等效盡量轉(zhuǎn)換成與門,或門的組合2.觀察版圖結(jié)構(gòu),不管在PMOS還是NMOS區(qū)域,器件結(jié)構(gòu)出現(xiàn)為串聯(lián)結(jié)構(gòu),即可通過冗余設(shè)計(jì)進(jìn)行來加強(qiáng)脈沖窄化,抵御單粒子脈沖。最后,本文對脈沖窄化在更小的工藝尺寸的應(yīng)用和NMOS器件的防護(hù)設(shè)計(jì)的研究方向進(jìn)行展望。
[Abstract]:With the development of integrated circuits towards smaller process size, higher integration, the impact of particle incidence in radiation environment is becoming more and more serious. The single particle effect caused by particle incidence has become one of the most important reasons for the failure of aerospace circuits. The reduction of process size reduces the distance between nodes, resulting in more and more charge sharing between nodes when single particle bombardment occurs. The multi-bit flip caused by this causes some traditional anti-radiation design methods, such as increasing the distance between devices, protection ring and so on, to invalidate the traditional anti-radiation design methods. The pulse narrowing effect based on charge sharing and multi-bit inversion is a new design idea of radiation protection. Based on 90 nm and 65 nm CMOS double well process, The layout Design method of basic Logic Circuits in 90 nm process based on Pulse narrowing the layout Design method of compound Logic Circuits under 65 nm process Radiation circuit layout design method. The application conditions and criteria of pulse narrowing in layout design are summarized. The main contents are as follows: 1) 3D device modeling and simulation of 90 nm process and 65 nm process are carried out by TCAD software. Under 90 nm process, different device spacing and LET value of incident particles were set. This paper explains the bimodal voltage phenomenon at the output node in the case of large device spacing or small incident particle LET value. Based on the working principle of pulse narrowing, this paper proposes a design method of redundant device which is suitable for pulse narrowing in PMOS layout, and redundancy design method in NMOS layout part of gate. A minimum spacing design method and an insensitive viewpoint of high LET value devices are proposed to compare the experimental results of the gate PMOS part at 90 nm and 65 nm particles. It is proposed that with the reduction of the process size of the device or the use of traditional layout in the PMOS part of the gate, the single particle pulse can be resisted without redundancy. Comparing with the experimental results of the gate NMOS part at 90 nm and 65 nm particle incidence, it is proposed that with the reduction of the device process size, the effect of using redundant design with the NMOS part of the gate will be better and better in the 65 nm process. The three-dimensional model simulation experiment of compound logic circuit is carried out. Comparing the two methods of logic equivalent circuit replacement and redundant design of compound logic circuit, it is proved that the redundancy design method is more excellent in design simplicity and stability. A proposal for applying the design method of pulse narrowing: 1. Complex logic circuit expressions should be converted as much as possible into gates, or combinations of gates, through logical equivalence. In the PMOS or NMOS region, the device structure appears in series structure, which can enhance the pulse narrowing by redundant design and resist the single particle pulse. Finally, the application of pulse narrowing in smaller process size and the research direction of NMOS device protection design are prospected.
【學(xué)位授予單位】：深圳大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN791

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