本文選題：FPGA + 脈沖壓縮�。� 參考：《中國航天科技集團(tuán)公司第一研究院》2017年碩士論文

【摘要】：傳統(tǒng)雷達(dá)信號處理機(jī)制將包括脈沖壓縮處理在內(nèi)的整套雷達(dá)成像算法放在DSP中完成,在處理點(diǎn)數(shù)多,數(shù)據(jù)量大的情況下DSP受限于其內(nèi)存空間,難以獨(dú)自完成整套成像算法,且其順序執(zhí)行指令的處理機(jī)制,也使得其進(jìn)行大點(diǎn)數(shù)脈沖壓縮處理的實(shí)時性較差。本文針對現(xiàn)代雷達(dá)系統(tǒng)工作模式多、處理數(shù)據(jù)量大的特點(diǎn),提出一種基于FPGA處理平臺,集信號采集、預(yù)處理和脈沖壓縮于一身的高效脈沖壓縮系統(tǒng)方案。首先,本文就信號采集基本原理與量化誤差進(jìn)行了闡述,明確了利用數(shù)字采樣信號還原出原始模擬信號的條件,給出了理想情況下量化位數(shù)與信噪比的關(guān)系。隨后給出A/D轉(zhuǎn)換器的一些關(guān)鍵指標(biāo)的計算方法和物理意義,為硬件測試提供了依據(jù)。對AD芯片EV10AQ190A的功能、結(jié)構(gòu)和校正方法進(jìn)行了詳細(xì)闡述,對其關(guān)鍵性能指標(biāo)進(jìn)行了測試,其AD有效位數(shù)可達(dá)7.7位以上,無雜散動態(tài)范圍為45dB以上。其次,本文對多相濾波結(jié)構(gòu)的數(shù)學(xué)表達(dá)和物理構(gòu)架進(jìn)行了詳細(xì)的推導(dǎo)與描述,體現(xiàn)了其在工程應(yīng)用中的優(yōu)越性。并基于理論分析將多相濾波結(jié)構(gòu)運(yùn)用于數(shù)字正交下變頻的濾波抽取環(huán)節(jié),優(yōu)化了濾波器結(jié)構(gòu),有效地提高了處理效率。本文還結(jié)合了工程實(shí)例,對多相濾波結(jié)構(gòu)的處理效果進(jìn)行了軟件仿真和硬件驗證,結(jié)果證明基于多相濾波結(jié)構(gòu)的預(yù)處理能夠有效地實(shí)現(xiàn)防混疊、降速率和減少數(shù)據(jù)處理量的功能,且均能達(dá)到設(shè)計的預(yù)期效果和實(shí)用要求。再次,針對系統(tǒng)的核心功能,本文提出了一種基于復(fù)合FFT結(jié)構(gòu)的頻域脈沖壓縮法。其FFT模塊采用復(fù)式FFT結(jié)構(gòu),運(yùn)算能力比基-4 Burst I/O結(jié)構(gòu)提高了一倍;參考函數(shù)模塊采用實(shí)時查表法,根據(jù)發(fā)射信號基本參數(shù)對參考信號進(jìn)行實(shí)時生成。在Matlab和ISE平臺上進(jìn)行仿真,結(jié)果表明該方法能夠高效地實(shí)現(xiàn)32768點(diǎn)脈沖壓縮處理,處理點(diǎn)數(shù)多,實(shí)時性高,相同處理點(diǎn)數(shù)下其處理時間不到TMS320C6678型DSP耗時的一半,且處理結(jié)果滿足工程應(yīng)用要求。最后,本文將脈沖壓縮模塊封裝成IP核,在以Virtex-7 FPGA為核心處理器的硬件平臺上對整個高效脈沖壓縮系統(tǒng)的性能進(jìn)行驗證。結(jié)果證明該系統(tǒng)能夠高效實(shí)時的完成多模式脈沖壓縮的功能,在脈沖壓縮體制的小型化雷達(dá)處理機(jī)中有很大的應(yīng)用價值。
[Abstract]:In the traditional radar signal processing mechanism, the whole radar imaging algorithm, including pulse compression processing, is put into DSP. In the case of large number of processing points and large amount of data, DSP is limited by its memory space, so it is difficult to complete the whole imaging algorithm alone. The processing mechanism of its sequential execution instruction also makes the processing of large number pulse compression worse in real time. In view of the characteristics of the modern radar system, which has many working modes and large amount of data, this paper presents an efficient pulse compression system based on FPGA processing platform, which integrates signal acquisition, preprocessing and pulse compression. Firstly, the basic principle of signal acquisition and quantization error are expounded, and the condition of reducing the original analog signal by using digital sampling signal is clarified, and the relationship between quantization bit number and SNR under ideal condition is given. Then the calculation method and physical meaning of some key indexes of the A / D converter are given, which provides the basis for the hardware test. The function, structure and correction method of AD chip EV10AQ190A are described in detail. The key performance indexes of AD chip are tested. The effective bit number of AD chip is more than 7.7 bits, and the range of no stray dynamic is more than 45dB. Secondly, the mathematical expression and physical framework of the polyphase filter structure are derived and described in detail, which reflects its superiority in engineering application. Based on the theoretical analysis, the polyphase filter structure is applied to the filtering and decimation of digital orthogonal down-conversion, the filter structure is optimized, and the processing efficiency is improved effectively. The software simulation and hardware verification of the multiphase filter structure are also carried out with an engineering example. The results show that the preprocessing based on the multiphase filter structure can effectively achieve anti-aliasing. The function of reducing the rate and reducing the data processing can reach the expected effect and practical requirement of the design. Thirdly, a frequency domain pulse compression method based on compound FFT structure is proposed for the core functions of the system. The FFT module uses the compound FFT structure, and its computing power is twice as high as that of the base -4 Burst I / O structure. The reference function module uses the real-time lookup table method to generate the reference signal in real time according to the basic parameters of the transmitted signal. The simulation results on Matlab and ISE platform show that the proposed method can efficiently realize 32768 point pulse compression processing, which has many points and high real-time performance. The processing time of the same processing points is less than half of that of TMS320C6678 DSP. The results meet the requirements of engineering application. Finally, the pulse compression module is encapsulated into IP core, and the performance of the high efficiency pulse compression system is verified on the hardware platform with Virtex-7 FPGA as the core processor. The results show that the system can efficiently and real-time complete the function of multi-mode pulse compression, and has great application value in the miniaturized radar processor of pulse compression system.
【學(xué)位授予單位】：中國航天科技集團(tuán)公司第一研究院
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN791;TN957.51

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 蘇海;張群英;葉盛波;張曉娟;方廣有;;基于FPGA內(nèi)嵌DSP硬核的脈沖壓縮設(shè)計與實(shí)現(xiàn)[J];電子測量技術(shù);2016年09期

2 顧峰;戴健;;一種基于FPGA的頻域脈沖壓縮處理器的實(shí)現(xiàn)[J];艦船電子對抗;2016年04期

3 賈穎燾;顧趙宇;傅其詳;王偉;;基于FPGA和DSP的雷達(dá)信號脈沖壓縮[J];現(xiàn)代電子技術(shù);2015年17期

4 肖漢波;;基于EV10AQ190的高速ADC接口設(shè)計[J];電子器件;2015年03期

5 王靜;朱劍;杜科;;寬帶正交解調(diào)和脈沖壓縮優(yōu)化處理及FPGA實(shí)現(xiàn)[J];制導(dǎo)與引信;2015年01期

6 楊守峰;秦慶兵;余開;;基于通用硬件的數(shù)字脈沖壓縮工程實(shí)現(xiàn)研究[J];電子科技;2015年01期

7 唐愛鵬;劉麗霞;倪亮;;線性調(diào)頻信號數(shù)字脈沖壓縮的優(yōu)化設(shè)計[J];計算機(jī)仿真;2014年08期

8 蘇斌;劉暢;;基于FPGA的脈沖壓縮處理器設(shè)計與實(shí)現(xiàn)[J];電子測量技術(shù);2014年07期

9 龐龍;陳禾;;基于FPGA的數(shù)字脈沖壓縮系統(tǒng)實(shí)現(xiàn)[J];現(xiàn)代電子技術(shù);2010年14期

10 王超;田黎育;高梅國;;基于FPGA的高速數(shù)字脈沖壓縮[J];計算機(jī)工程;2008年04期

相關(guān)會議論文 前1條

1 高立寧;龍騰;;基于FPGA的星上實(shí)時信息處理系統(tǒng)[A];全國第二屆信號處理與應(yīng)用學(xué)術(shù)會議專刊[C];2008年

相關(guān)博士學(xué)位論文 前1條

1 王國慶;寬帶雷達(dá)直接解調(diào)原理與實(shí)時脈壓技術(shù)研究[D];國防科學(xué)技術(shù)大學(xué);2011年

相關(guān)碩士學(xué)位論文 前10條

1 劉霄;調(diào)頻信號脈沖壓縮的FPGA實(shí)現(xiàn)[D];北京理工大學(xué);2016年

2 何芹;高速高精度ADC頻域特性測試方法研究[D];江南大學(xué);2015年

3 李志華;基于FPGA的微型SAR實(shí)時成像處理研究[D];西安電子科技大學(xué);2014年

4 閻煒;數(shù)字下變頻器和脈沖壓縮的研究與設(shè)計[D];西安電子科技大學(xué);2014年

5 鄧一琨;基于FPGA數(shù)字脈沖壓縮技術(shù)研究和仿真系統(tǒng)實(shí)現(xiàn)[D];電子科技大學(xué);2011年

6 鄭程;基于FPGA的數(shù)字下變頻與數(shù)字脈沖壓縮技術(shù)研究[D];哈爾濱工業(yè)大學(xué);2011年

7 于大衛(wèi);基于FPGA的多相濾波結(jié)構(gòu)研究與實(shí)現(xiàn)[D];大連海事大學(xué);2008年

8 潘琳;基于FPGA的雷達(dá)脈沖壓縮系統(tǒng)的研究與實(shí)現(xiàn)[D];上海交通大學(xué);2008年

9 曹俊文;寬帶實(shí)時脈沖壓縮技術(shù)研究與實(shí)現(xiàn)[D];華中科技大學(xué);2008年

10 宋奇菊;雷達(dá)脈沖壓縮處理高效算法與關(guān)鍵技術(shù)研究[D];電子科技大學(xué);2008年

，

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