發(fā)布時(shí)間：2018-05-14 10:43

  本文選題：硅通孔(TSV) + 熱機(jī)械可靠性　； 參考：《華中科技大學(xué)》2015年碩士論文

【摘要】：近年來(lái),微電子行業(yè)快速發(fā)展,對(duì)于電子產(chǎn)品的封裝要求也越來(lái)越高,就促使封裝行業(yè)的關(guān)鍵技術(shù)獲得進(jìn)一步改進(jìn),其中硅通孔技術(shù)的出現(xiàn)將封裝業(yè)帶入了一個(gè)新的轉(zhuǎn)折點(diǎn),但是隨著尺寸的微細(xì)化,硅通孔技術(shù)作為一項(xiàng)新的技術(shù),也存在很多問(wèn)題,考慮到封裝的疲勞和失效,其中對(duì)于三維堆疊封裝結(jié)構(gòu)的熱可靠性分析成為了該項(xiàng)技術(shù)發(fā)展的關(guān)鍵。為了避免封裝結(jié)構(gòu)關(guān)鍵部位在熱載荷的作用下發(fā)生熱變形失效,本文進(jìn)行了以下幾個(gè)方面的研究。首先,研究了電鍍銅使用不同的材料屬性參數(shù),單個(gè)硅通孔在熱沖擊溫度載荷下的熱機(jī)械響應(yīng)。經(jīng)過(guò)多次有限元分析,得出兩者應(yīng)力大小和分布的不同,總結(jié)應(yīng)力大小分布發(fā)生的機(jī)理,進(jìn)一步研究了結(jié)構(gòu)參數(shù)對(duì)于單個(gè)硅通孔熱機(jī)械可靠性的影響。對(duì)比了相同結(jié)構(gòu)參數(shù)下單個(gè)硅通孔在二維模型和三維模型下的分析結(jié)果。經(jīng)過(guò)多次建模分析,得出了在兩種模型下,硅通孔的應(yīng)力大小和分布的相同點(diǎn)和不同點(diǎn)。其次,用解析法和數(shù)值方法聯(lián)合研究二維俯視圖和軸向圖簡(jiǎn)化結(jié)構(gòu)的適用范圍,通過(guò)探究得出,芯片堆疊封裝用二維軸向模型可以相對(duì)準(zhǔn)確的反映堆疊芯片之間熱應(yīng)力的相互影響。最后,建立了多層堆疊芯片的二維軸向簡(jiǎn)化模型,研究了其整體變形以及關(guān)鍵部位的應(yīng)力分布和大小,并研究了結(jié)構(gòu)參數(shù),包括芯片中硅通孔直徑、微焊點(diǎn)高度、中介層中硅通孔直徑、中介層厚度和常規(guī)焊點(diǎn)高度對(duì)其熱應(yīng)力的影響曲線圖。通過(guò)本文研究,為硅通孔的設(shè)計(jì)提供科學(xué)的理論依據(jù),對(duì)電子封裝行業(yè)的發(fā)展具有深遠(yuǎn)的社會(huì)意義。
[Abstract]:In recent years, with the rapid development of the microelectronics industry, the packaging requirements for electronic products are becoming higher and higher. The key technologies of the packaging industry have been further improved. The emergence of silicon through hole technology has brought the packaging industry into a new turning point. However, as a new technology, silicon through hole technology has many problems. Considering the fatigue and failure of packaging, the thermal reliability analysis of three-dimensional stacked packaging structure becomes the key to the development of this technology. In order to avoid the thermal deformation failure of the key parts of the packaging structure under thermal load, the following aspects are studied in this paper. Firstly, the thermal mechanical response of single silicon through hole under thermal shock temperature load with different properties of copper electroplating was studied. After many finite element analysis, the difference of stress size and distribution between them is obtained. The mechanism of stress distribution is summarized, and the influence of structural parameters on the thermal mechanical reliability of a single silicon through hole is further studied. The results of two dimensional model and three dimensional model are compared. After several modeling and analysis, the similarities and differences of the stress size and distribution of the through hole in the two models are obtained. Secondly, using the analytical method and numerical method to study the application range of the simplified structure of the two-dimensional overlooking map and the axial chart, it is concluded that, Two-dimensional axial model for chip stacking packaging can reflect the interaction of thermal stress between stacked chips relatively accurately. Finally, the two-dimensional axial simplified model of multilayer stacked chip is established, and the global deformation, stress distribution and size of key parts are studied, and the structural parameters, including the diameter of silicon through hole and the height of micro-solder joint in the chip, are studied. The influence of the diameter of the through hole, the thickness of the interlayer and the height of the conventional solder joint on the thermal stress in the interlayer. Through the research in this paper, it provides a scientific theoretical basis for the design of silicon through hole, and has far-reaching social significance for the development of electronic packaging industry.
【學(xué)位授予單位】：華中科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN05

【參考文獻(xiàn)】

相關(guān)期刊論文 前4條

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本文編號(hào)：1887545