本文選題：差分功耗分析(DPA) + 物理不可克隆函數(shù)(PUF)��； 參考：《寧波大學(xué)》2017年碩士論文

【摘要】：隨著信息安全和集成電路技術(shù)的不斷發(fā)展,以密碼芯片為核心部件的便攜式設(shè)備在日常生活中得到廣泛應(yīng)用,如網(wǎng)上銀行、智能卡等,給人們的生活提供了許多便利。然而,密碼芯片在處理不同數(shù)據(jù)時(shí),其能量消耗、運(yùn)行時(shí)間和電磁輻射等物理信息與所處理的數(shù)據(jù)具有相關(guān)性。于是,攻擊者通常利用這些物理信息對(duì)密碼芯片實(shí)施旁道攻擊(Side Channel Attack,SCA)可獲取密鑰信息。在一系列旁道攻擊技術(shù)中,差分功耗分析(Differential Power Analysis,DPA)技術(shù)是一種常見(jiàn)且簡(jiǎn)單高效的旁道攻擊方法,已經(jīng)嚴(yán)重威脅到密碼芯片的信息安全。因此各類抗DPA攻擊的功耗獨(dú)立技術(shù)應(yīng)運(yùn)而生,本文主要研究物理不可克隆函數(shù)(Physical Unclonable Functions,PUF)電路和靈敏放大型邏輯(Sense Amplifier Based Logic,SABL)電路,實(shí)現(xiàn)高效的防御DPA攻擊。PUF電路是芯片領(lǐng)域的“DNA特征識(shí)別技術(shù)”,通過(guò)提取芯片復(fù)雜的物理特性產(chǎn)生無(wú)限多個(gè)唯一的、隨機(jī)的和不可預(yù)測(cè)的密鑰,實(shí)現(xiàn)輸出數(shù)據(jù)只與工藝偏差有關(guān),與功耗無(wú)關(guān)。SABL電路是一種動(dòng)態(tài)雙軌預(yù)充電路,其通過(guò)引入預(yù)充電技術(shù)使電路輸出具有恒定的翻轉(zhuǎn)率,從而具有功耗恒定的特性,理論上可以完全消除電路功耗與所處理數(shù)據(jù)的相關(guān)性。研究?jī)?nèi)容主要包含以下幾個(gè)部分:1.基于電橋失衡效應(yīng)的PUF電路設(shè)計(jì):首先通過(guò)對(duì)電橋失衡效應(yīng)的分析,結(jié)合PUF電路的設(shè)計(jì)特點(diǎn),將由于工藝偏差所導(dǎo)致失衡的四臂電橋作為偏差信號(hào)產(chǎn)生電路,從而得到兩路隨機(jī)偏差電壓,然后利用電壓型靈敏放大器比較輸入的偏差電壓大小,產(chǎn)生輸出信號(hào),進(jìn)而實(shí)現(xiàn)具有高隨機(jī)性的PUF電路。2.基于單穩(wěn)態(tài)定時(shí)偏差的PUF電路設(shè)計(jì):首先分析單穩(wěn)態(tài)定時(shí)電路的自我標(biāo)識(shí)物理特性及失配情況,提出長(zhǎng)定時(shí)單穩(wěn)態(tài)電路設(shè)計(jì)方法,然后利用該單穩(wěn)態(tài)電路產(chǎn)生定時(shí)偏差信號(hào)以及激勵(lì)信號(hào)控制數(shù)據(jù)選擇器選擇兩個(gè)定時(shí)偏差信號(hào),結(jié)合SR仲裁器判決輸出信號(hào),最終實(shí)現(xiàn)具有高識(shí)別性的PUF電路。3.基于SABL的抗DPA攻擊可重構(gòu)加法器設(shè)計(jì):通過(guò)對(duì)傳統(tǒng)超前進(jìn)位加法器原理的研究,根據(jù)SABL電路工作特點(diǎn)設(shè)計(jì)出具有抗DPA攻擊性能的4位超前進(jìn)位加法器電路,然后利用該4位超前進(jìn)位加法器電路構(gòu)成16位可重構(gòu)超前進(jìn)位加法器電路,實(shí)現(xiàn)支持4個(gè)8位數(shù)據(jù)或2個(gè)16位數(shù)據(jù)的加法運(yùn)算電路。4.基于SABL的抗DPA攻擊移位寄存器設(shè)計(jì):通過(guò)對(duì)傳統(tǒng)移位寄存器和SABL單元電路原理的研究,根據(jù)主從觸發(fā)器的原理設(shè)計(jì)具有清零置位功能的D觸發(fā)器電路,然后利用該觸發(fā)器電路及SABL邏輯門(mén)實(shí)現(xiàn)能夠防御差分功耗分析、具有左移右移并入并出功能4位移位寄存器電路。本文所提出的電路方案均采用TSMC 65nm CMOS工藝參數(shù)設(shè)計(jì),并利用Spectre等工具對(duì)電路進(jìn)行仿真驗(yàn)證。結(jié)果表明所設(shè)計(jì)的電路邏輯功能正確,相關(guān)性能指標(biāo)有明顯的優(yōu)化。
[Abstract]:With the development of information security and integrated circuit technology, portable devices based on cipher chips have been widely used in daily life, such as online banking, smart cards and so on. However, when the cipher chip processes different data, its physical information, such as energy consumption, running time and electromagnetic radiation, is correlated with the processed data. Therefore, attackers usually use these physical information to carry out bypass attack on cryptographic chip side Channel attack (SCA) to obtain key information. Among a series of bypass attack techniques, differential Power Analysis (DPA) is a common and simple and efficient bypass attack method, which has seriously threatened the information security of cryptographic chips. Therefore, various power independent techniques against DPA attacks have emerged. In this paper, we mainly study physical Unclonable functions (PUFs) circuits and sense Amplifier Based logic (SABLs) circuits. The efficient protection against DPA attack. PUF circuit is the "DNA feature recognition technology" in the chip field, which generates infinite unique, random and unpredictable keys by extracting the complex physical characteristics of the chip. The output data is only related to the process deviation, and the power consumption independent. SABL circuit is a kind of dynamic dual track precharge circuit. By introducing precharge technology, the output of the circuit has a constant turnover rate, which has the characteristic of constant power consumption. Theoretically, the correlation between circuit power consumption and the data processed can be completely eliminated. The research mainly includes the following parts: 1. PUF circuit design based on bridge imbalance effect: firstly, through the analysis of bridge imbalance effect, combined with the design characteristics of PUF circuit, the four-arm bridge which is out of balance due to process deviation is used as the bias signal generation circuit. Two random bias voltages are obtained, and then the input bias voltage is compared with the voltage source sensitive amplifier to generate the output signal, and then the high randomness PUF circuit. 2. Design of PUF Circuit based on Monostable timing deviation: firstly, the self-identification physical characteristics and mismatch of Monostable timing circuit are analyzed, and the design method of long time Monostable Circuit is proposed. Then, two timing bias signals are selected by using the Monostable circuit and the excitation signal control data selector, and finally the highly recognizable PUF circuit. 3 is realized by combining with the SR arbiter decision output signal. The design of reconfigurable adder against DPA attack based on SABL: through the study of the principle of traditional carry adder, according to the working characteristics of SABL circuit, a 4-bit carry-adder circuit with anti-DPA attack performance is designed. Then the 4-bit carry-ahead adder circuit is used to construct the 16-bit reconfigurable carry-ahead adder circuit, which supports four 8-bit data or two 16-bit data. The design of anti-DPA attack shift register based on SABL: by studying the traditional shift register and the principle of SABL cell circuit, according to the principle of master-slave flip-flop, the D-flip-flop circuit with zero setting function is designed. Then the flip-flop circuit and the SABL logic gate are used to implement the differential power analysis, and the four-bit shift register circuit with the function of left shift and right shift merging and output function is realized. In this paper, TSMC 65nm CMOS process parameters are used to design the circuit, and Spectre is used to verify the circuit. The results show that the logic function of the designed circuit is correct and the related performance indexes are obviously optimized.
【學(xué)位授予單位】：寧波大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN402

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