本文選題：碳化硅 + MOSFETs�。� 參考：《電子科技大學(xué)》2017年碩士論文

【摘要】：碳化硅(SiC)優(yōu)良的材料特性,使其十分適用于制作大功率高速的開(kāi)關(guān)器件,例如金屬-氧化物-半導(dǎo)體場(chǎng)效應(yīng)晶體管(MOSFETs)。目前國(guó)內(nèi)諸多研究小組已經(jīng)展開(kāi)了SiC MOSFETs的研制,然而國(guó)內(nèi)研制的這批器件正向電流特性普遍較差。本文立足于國(guó)內(nèi)碳化硅工藝實(shí)驗(yàn)平臺(tái),開(kāi)展高壓大電流SiC MOSFETs晶體管的結(jié)構(gòu)設(shè)計(jì)和關(guān)鍵工藝技術(shù)研究。本文首先利用Silvaco仿真軟件對(duì)SiC MOSFETs器件的元胞結(jié)構(gòu)進(jìn)行仿真設(shè)計(jì),主要通過(guò)設(shè)計(jì)優(yōu)化影響導(dǎo)通器件電阻的相關(guān)參數(shù),在最優(yōu)化正向電流特性的同時(shí)滿足耐壓要求且避免產(chǎn)生寄生效應(yīng);之后為滿足制作工藝的需求對(duì)器件終端結(jié)構(gòu)進(jìn)行了重新設(shè)計(jì)優(yōu)化。其次開(kāi)展了大電流SiC MOSFETs晶體管關(guān)鍵工藝實(shí)驗(yàn)研究,主要包括:滿足短溝道制作需求的SiC MOSFETs自對(duì)準(zhǔn)工藝;為降低降低源接觸電阻,開(kāi)發(fā)出基于Ni金屬的碳化硅P/N型歐姆合金工藝;為減少SiC/SiO_2界面態(tài)密度,摸索了將干法氧化和濕法氧化相結(jié)合的柵氧化工藝;為增強(qiáng)SiC MOSFETs柵ESD保護(hù),設(shè)計(jì)并實(shí)驗(yàn)驗(yàn)證了工藝兼容的多晶硅二極管ESD結(jié)構(gòu)。最后整合成熟的制作工藝,開(kāi)展了大電流1200V 4H-SiC MOSFETs晶體管的流片實(shí)驗(yàn)。實(shí)驗(yàn)樣品測(cè)試結(jié)果表明:采用非自對(duì)準(zhǔn)工藝制作的器件正向電流26A@VGS=20V;采用自對(duì)準(zhǔn)工藝制作的器件正向電流34A@VGS=20V。同時(shí),利用研制的橫向SiC MOSFETs晶體管提取了器件的反型層溝道遷移率,遷移率約為20 cm2/V·s。本文基于國(guó)內(nèi)的SiC器件工藝試驗(yàn)平臺(tái),通過(guò)對(duì)高壓大電流SiC MOSFETs晶體管的結(jié)構(gòu)設(shè)計(jì)和關(guān)鍵工藝技術(shù)研究,實(shí)現(xiàn)了1200V/30A SiC MOSFETs晶體管樣品的研制,為國(guó)內(nèi)高壓大電流4H-SiC MOSFETs器件的研制提供了參考。
[Abstract]:Because of its excellent material properties, sic is very suitable for high power and high speed switching devices, such as metal-oxide-semiconductor field effect transistors (MOSFETs). At present, many domestic research groups have developed SiC MOSFETs. However, the forward current characteristics of these devices are generally poor. Based on the experimental platform of silicon carbide process in China, the structure design and key technology of high-voltage and high-current SiC MOSFETs transistors are studied in this paper. In this paper, the cellular structure of SiC MOSFETs devices is designed by using Silvaco simulation software, and the parameters that affect the resistance of the devices are optimized. In order to optimize the forward current characteristics and avoid parasitic effect, the device terminal structure is redesigned and optimized to meet the requirements of fabrication process. Secondly, the key process experiments of high current SiC MOSFETs transistors are carried out, including: the SiC MOSFETs self-alignment process to meet the needs of short channel fabrication, the development of silicon carbide P / N ohmic alloy process based on Ni metal in order to reduce the source contact resistance. In order to reduce the density of interfacial states of SiC/SiO_2, the gate oxidation process combining dry and wet oxidation was explored, and the ESD structure of polycrystalline silicon diode was designed and experimentally verified to enhance the protection of SiC MOSFETs gate ESD. Finally, the wafer experiment of 1200V 4H-SiC MOSFETs transistor with high current is carried out by integrating the mature fabrication technology. The experimental results show that the forward current of the device made by the off-alignment process is 26AVGSN 20V, and that of the device fabricated by the self-aligned process is 34AVGS- 20V. At the same time, the transversal layer channel mobility of the device is extracted by using the developed transverse SiC MOSFETs transistor, and the mobility is about 20 cm2/V s. Based on the SiC device process test platform in China, the structure design and key technology of SiC MOSFETs transistor with high voltage and high current are studied in this paper, and the sample of 1200V/30A SiC MOSFETs transistor is developed. It provides a reference for the development of high voltage and high current 4H-SiC MOSFETs devices in China.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN386

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本文編號(hào)：1872627