發(fā)布時間：2018-05-07 20:38

  本文選題：電源管理芯片 + 漏電流��； 參考：《大連理工大學(xué)》2015年碩士論文

【摘要】：電源管理芯片是每部移動電子設(shè)備不可或缺的部分,它直接影響著移動電子設(shè)備的功耗和待機時間。在設(shè)計和制造工藝交互作用下產(chǎn)生的缺陷所造成的漏電流失效是制約電源管理芯片產(chǎn)品良率的主要因素。在芯片能夠批量上市之前,它首先必須達到能以可接受的良率(Yield)進行批量制造的水平。但從集成電路設(shè)計到工藝制造存在一個良率逐步提升的過程,需要一定的時間。芯片的設(shè)計驗證完成時間還要再加上這個良率時間才是真正的產(chǎn)品上市時間,因此良率的快速提升成為集成電路芯片設(shè)計公司打開市場,獲得利潤的迫切要求。本文選取一款市面在用的移動電子設(shè)備上的電源管理芯片開展漏電流失效分析及良率提升研究。在數(shù)據(jù)分析方面,抽樣出100片晶圓,對它的漏電流針測(Chip Probe, CP)并對采樣數(shù)據(jù)采用累積疊加分布的方式制作分布圖。在電性分析方面,采用4156C(精密半導(dǎo)體參數(shù)分析儀)測量I-V曲線,采用紅外發(fā)光顯微鏡(Emission Microscopy, EMMI)和激光誘導(dǎo)電阻率變化測試儀(Optical Beam Induced Resistance Change, OBIRCH)定位缺陷位置。然后用原子力顯微鏡(Atomic Force Microscopy, AFM)和納米探針系統(tǒng)(NanoProbe)分析失效模式。在物理分析方面,采用物理剝層、聚焦離子束顯微鏡(Focused Ion Beam, FIB)、掃描電鏡(Scanning Electron Microscope, SEM)、缺陷化學(xué)成分分析和電壓襯度(Voltage Contrast, VC)定位技術(shù)來建立失效模型。通過研究,找到了該芯片的失效根源,配合生產(chǎn)線研究失效的產(chǎn)生機理,找出了良率提升的辦法。
[Abstract]:Power management chip is an indispensable part of every mobile electronic device. It directly affects the power consumption and standby time of mobile electronic device. The leakage current failure caused by the defects caused by the interaction of design and manufacturing process is the main factor that restricts the yield of power management chip products. Before the chip can be mass-produced, it must first reach the level of mass manufacturing with acceptable yield yield. However, from IC design to process manufacturing, there is a process of increasing yield, which will take a certain amount of time. The completion time of chip design verification must be coupled with this yield time which is the real time to market. Therefore, the rapid improvement of yield becomes the urgent requirement for IC chip design companies to open up the market and make profits. In this paper, a power management chip for mobile electronic devices in use is selected to study leakage current failure and yield enhancement. In the aspect of data analysis, 100 wafers are sampled, and its leakage current needle is used to measure Chip Probe (CPP), and the distribution map is made by accumulative superposition distribution of the sample data. The I-V curve was measured by 4156C (Precision Semiconductor Parameter Analyzer), and the defect position was located by infrared luminescence microscope (EMMI) and laser-induced resistivity change tester (Beam Induced Resistance Change, OBIRCH). Then atomic Force microscopy (AFM) and nanometer probe system (Nano Probe) were used to analyze the failure mode. In terms of physical analysis, failure models were established by physical stripping, focusing ion beam microscope, focused Ion beam, scanning electron microscopy, scanning Electron microscope, SEMU, defect chemical composition analysis and voltage contrast (VC) localization techniques. Through the research, the cause of failure of the chip is found, and the mechanism of the failure is studied with the production line, and the method of improving the yield is found.
【學(xué)位授予單位】：大連理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN405

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