本文選題：光纖通道協(xié)議 + 光纖鏈路激活　； 參考：《電子科技大學》2015年碩士論文

【摘要】：隨著大數(shù)據(jù)時代的來臨,海量數(shù)據(jù)的傳輸和存儲對互聯(lián)通信方式提出了傳輸速率更高,帶寬更大,傳輸方式更便捷更安全等要求�；诟咚倩ヂ�(lián)傳輸?shù)目偩�技術(shù)已經(jīng)發(fā)展成為多種類,多速率方式。光纖通道技術(shù)憑借超高速的傳輸速率(最高可達到10Gbps的傳輸速率),良好的抗干擾性能,穩(wěn)定的傳輸質(zhì)量等特點成為高速互聯(lián)領(lǐng)域研究的熱點。論文通過對當前光纖通道技術(shù)發(fā)展的研究,以及對高速數(shù)據(jù)傳輸需求的分析,選擇了光纖通道技術(shù)第三類服務(wù)作為本文的設(shè)計對象。在詳細分析光纖通道協(xié)議體系結(jié)構(gòu)的基礎(chǔ)上,結(jié)合可編程邏輯器件(FPGA芯片)架構(gòu)靈活、適合進行高速總線開發(fā)的特點,提出了在ALTERA Stratix IV芯片中進行Fibre-channel協(xié)議設(shè)計的方案。Fibre-channel協(xié)議的邏輯設(shè)計全部采用Verilog硬件描述語言完成,論文詳細闡述了FC-0層,FC-1層,FC-2層的功能設(shè)計與實現(xiàn)過程,完成了最高8.5Gbps的數(shù)據(jù)傳輸指標,并支持點到點拓撲的第三類服務(wù)。本文的主要設(shè)計內(nèi)容包括:(1)通過設(shè)計SFP+光模塊和Stratix IV中的高速串行收發(fā)器實現(xiàn)FC-0層功能,將高速串行的光纖鏈路數(shù)據(jù)轉(zhuǎn)變成40bit的低速并行的通路數(shù)據(jù);(2)通過設(shè)計8B/10B編解碼、傳輸字邊界對齊、同步狀態(tài)機和端口狀態(tài)機,實現(xiàn)對原語數(shù)據(jù)的對齊操作,并將對齊的數(shù)據(jù)送入同步狀態(tài)機完成同步檢測,同步原語數(shù)據(jù)送入端口狀態(tài)機進行鏈路狀態(tài)的推進,直至實現(xiàn)光纖鏈路的激活,完成FC-1層規(guī)定的功能;(3)當鏈路實現(xiàn)激活之后,論文通過幀發(fā)送狀態(tài)機設(shè)計,將數(shù)據(jù)按照標準的幀格式進行組裝和發(fā)送,實現(xiàn)FC-2層中幀的發(fā)送和接收;(4)通過設(shè)計鏈路擴展服務(wù)數(shù)據(jù)幀的交互來實現(xiàn)雙方端口的通信參數(shù)協(xié)商,在FC-2層實現(xiàn)架構(gòu)登錄,端口登錄,進程登錄和端口注銷等設(shè)計;(5)基于緩沖區(qū)到緩沖區(qū)的流量控制策略設(shè)計,實現(xiàn)對幀接收和幀發(fā)送的控制,完成對整個通信狀態(tài)的控制。論文最后對光纖通道系統(tǒng)的各個模塊進行了相應(yīng)的仿真和測試,測試包括了板級時域信號測試和各模塊的邏輯測試。論文通過對高速收發(fā)器的初始化、端口狀態(tài)機交互、幀合成與幀傳輸、架構(gòu)登錄、端口登錄、進程登錄等幾個過程的測試結(jié)果進行分析,驗證了光纖鏈路的激活、登錄與注冊狀態(tài)、流量控制策略等設(shè)計達到了指標要求。
[Abstract]:With the advent of big data era, the transmission and storage of mass data put forward the requirements of higher transmission rate, larger bandwidth, more convenient and more secure transmission mode. Bus technology based on high-speed interconnection has developed into multi-type and multi-rate mode. Fiber channel technology has become a hotspot in the field of high-speed interconnection with the characteristics of super high speed transmission rate (up to 10Gbps transmission rate), good anti-interference performance and stable transmission quality. Through the research on the development of optical fiber channel technology and the analysis of the demand for high-speed data transmission, the third kind of service of optical fiber channel technology is chosen as the design object of this paper. Based on the detailed analysis of fiber channel protocol architecture and the flexible architecture of programmable logic device (FPGA), it is suitable for high-speed bus development. The logic design of Fibre-channel protocol in ALTERA Stratix IV chip is presented. The logic design of Fibre-channel protocol is accomplished by Verilog hardware description language. The function design and implementation process of FC-0 layer FC-1 layer and FC-2 layer are described in detail in this paper. The data transmission index of the highest 8.5Gbps is completed, and the third kind of service of point-to-point topology is supported. The main design contents of this paper include: (1) realizing the function of FC-0 layer by designing SFP optical module and high speed serial transceiver in Stratix IV, converting high speed serial fiber link data into 40bit low speed parallel path data 2) designing 8B/10B codec. The transmission word boundary alignment, synchronous state machine and port state machine realize the alignment operation of primitive data, and the aligned data is sent into the synchronous state machine to complete synchronous detection, and the synchronous primitive data is sent into port state machine to push forward the link state. When the link is activated, the data is assembled and transmitted according to the standard frame format through the design of frame sending state machine. To realize the transmission and reception of frames in FC-2 layer, the communication parameters of both ports can be negotiated by designing the interaction of link extension service data frames, and the architecture login and port login are realized in the FC-2 layer. The design of process login and port logoff is based on the design of buffer to buffer flow control strategy, which can control frame receiving and frame sending, and complete the control of the whole communication state. At the end of the paper, the corresponding simulation and test of each module of fiber channel system are carried out. The test includes board level time domain signal test and logic test of each module. By analyzing the initialization of high-speed transceiver, port state machine interaction, frame synthesis and frame transmission, architecture login, port login, process login and so on, the paper verifies the activation of optical fiber link. Login and registration status, flow control strategy and other design reached the target requirements.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN791;TN915.04

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本文編號：1855411