本文選題：數(shù)字下變頻 + CORDIC算法��； 參考：《西安電子科技大學(xué)》2015年碩士論文

【摘要】：軟件無(wú)線(xiàn)電是無(wú)線(xiàn)通信的創(chuàng)新形式,并將推動(dòng)著無(wú)線(xiàn)通信領(lǐng)域的不斷創(chuàng)新。隨著軟件無(wú)線(xiàn)電的快速發(fā)展,該技術(shù)廣泛應(yīng)用于軍事和民用通信等領(lǐng)域,數(shù)字下變頻技術(shù)作為其關(guān)鍵技術(shù)之一,逐漸成為研究的焦點(diǎn)。FPGA是高速可配置的邏輯電路,具有可編程性、靈活性和高集成性等特點(diǎn)。基于FPGA實(shí)現(xiàn)數(shù)字下變頻,符合軟件無(wú)線(xiàn)電的靈活開(kāi)放要求。本文綜合考慮FPGA設(shè)計(jì)中的性能與成本的問(wèn)題,結(jié)合數(shù)字下變頻算法原理,采用級(jí)聯(lián)方式,根據(jù)每級(jí)的算法特點(diǎn),設(shè)計(jì)數(shù)字下變頻的高效實(shí)現(xiàn)結(jié)構(gòu)。本文主要研究?jī)?nèi)容如下:本文基于數(shù)字下變頻原理及其功能,完成了數(shù)字下變頻的RTL級(jí)設(shè)計(jì),并進(jìn)行了功能驗(yàn)證及邏輯綜合。首先,在多速率信號(hào)處理、CORDIC算法、DA算法和特殊濾波器算法等理論的基礎(chǔ)上,根據(jù)數(shù)字下變頻原理及其功能進(jìn)行系統(tǒng)規(guī)劃,將其劃分為兩個(gè)大模塊:下變頻模塊和抽取濾波器組模塊。然后,基于CORDIC算法設(shè)計(jì)了具有并行流水線(xiàn)結(jié)構(gòu)的下變頻模塊,通過(guò)一系列移位相加運(yùn)算,同時(shí)完成了數(shù)控振蕩器產(chǎn)生正余弦波樣本和混頻器的相乘功能,該結(jié)構(gòu)數(shù)據(jù)吞吐量大,節(jié)省了查找表和兩個(gè)并行乘法器。最后,依據(jù)抽取理論和多相分解技術(shù),結(jié)合抽取濾波器組模塊中各個(gè)模塊的算法特點(diǎn),完成了抽取濾波器組模塊中CIC抽取濾波器模塊、CIC補(bǔ)償濾波器模塊、HB濾波器模塊和FIR濾波器模塊的設(shè)計(jì)。其中,根據(jù)易位變換和Nobel恒等式原理,將CIC抽取濾波器模塊中的抽取操作放在積分器部分和梳狀濾波器部分之間,梳狀濾波器部分工作在較低的時(shí)鐘頻率下,所需的延遲單元數(shù)量顯著減少;利用濾波器系數(shù)對(duì)稱(chēng)性,采用DA算法結(jié)合抽取結(jié)構(gòu)來(lái)實(shí)現(xiàn)CIC補(bǔ)償濾波器模塊,采用DA算法結(jié)合多相結(jié)構(gòu)來(lái)實(shí)現(xiàn)HB濾波器模塊,這兩種結(jié)構(gòu)先進(jìn)行抽取,再進(jìn)行濾波運(yùn)算,避免了不必要的運(yùn)算,有效提高了運(yùn)算效率;FIR濾波器模塊采用串并結(jié)合的DA算法結(jié)構(gòu)來(lái)實(shí)現(xiàn),該結(jié)構(gòu)節(jié)約了硬件資源,并且提高了運(yùn)算速度。本論文采用MATLAB和Modelsim對(duì)設(shè)計(jì)的RTL級(jí)的數(shù)字下變頻進(jìn)行功能驗(yàn)證。其中,下變頻模塊中的CORDIC模塊計(jì)算正余弦函數(shù)的精度達(dá)到10-5數(shù)量級(jí)。將數(shù)字下變頻的處理結(jié)果與MATLAB模型的處理結(jié)果進(jìn)行對(duì)比,其相對(duì)誤差值達(dá)到10-5數(shù)量級(jí),該精度滿(mǎn)足設(shè)計(jì)要求。本文采用Synopsys公司的綜合工具Design Compiler,在SMIC 65nm的標(biāo)準(zhǔn)工藝庫(kù)下,對(duì)數(shù)字下變頻進(jìn)行了邏輯綜合,該數(shù)字下變頻的最大工作時(shí)鐘頻率為290.698MHz,綜合面積為99496.800420μm2。本設(shè)計(jì)具有可移植性,便于進(jìn)行系統(tǒng)的功能擴(kuò)展和升級(jí),有一定的研究參考價(jià)值。
[Abstract]:Software radio is an innovative form of wireless communication, and will promote the continuous innovation in the field of wireless communication. With the rapid development of software radio, this technology is widely used in military and civil communication fields. As one of its key technologies, digital down conversion technology has gradually become the focus of research. FPGA is a high speed configurable logic circuit. It has the characteristics of programmability, flexibility and high integration. Digital down conversion based on FPGA meets the flexible and open requirement of software radio. In this paper, the performance and cost of FPGA design are considered synthetically. Combining with the principle of digital down-conversion algorithm, the efficient realization structure of digital down-conversion is designed according to the algorithm characteristics of each stage by cascading method. The main contents of this paper are as follows: based on the principle and function of digital down conversion, the RTL level design of digital down conversion is completed, and the function verification and logic synthesis are carried out. Firstly, on the basis of the theory of multi-rate signal processing Cordic algorithm and special filter algorithm, the system planning is carried out according to the principle and function of digital down-conversion. It is divided into two modules: downconversion module and decimation filter bank module. Then, based on the CORDIC algorithm, a downconversion module with parallel pipeline structure is designed. By a series of shift addition operations, the numerical control oscillator produces the multiplication function of sinusoidal wave samples and mixers, and the data throughput of the structure is large. Save lookup table and two parallel multipliers. Finally, according to the decimation theory and the polyphase decomposition technology, combined with the algorithm characteristics of each module in the decimation filter bank module, The design of CIC decimation filter module and FIR filter module in decimation filter bank is completed. According to the principle of translocation transformation and Nobel identity, the decimation operation in the CIC decimation filter module is placed between the integrator part and the comb filter part, and the comb filter part works at a lower clock frequency. The number of delay units required is significantly reduced, the CIC compensation filter module is realized by using DA algorithm combined with decimation structure, and the HB filter module is implemented by DA algorithm combined with polyphase structure. These two kinds of structures are extracted first, then filtered to avoid unnecessary operation, and the efficiency of the Fir filter module is effectively improved by using the series-parallel DA algorithm structure, which saves the hardware resources. And the operation speed is improved. In this paper, MATLAB and Modelsim are used to verify the function of RTL level digital downconversion. Among them, the CORDIC module in the downconversion module can calculate the sinusoidal function with a precision of 10-5 orders of magnitude. The results of digital down-conversion are compared with those of MATLAB model. The relative error reaches 10-5 orders of magnitude, and the precision meets the design requirements. In this paper, we use Design Compiler, a synthetic tool of Synopsys Company, to synthesize the digital down-conversion under the standard process library of SMIC 65nm. The maximum working clock frequency of the digital down-conversion is 290.698MHz, and the synthetic area is 99496.800420 渭 m ~ 2. The design is portable, easy to expand and upgrade the system, and has a certain reference value.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN92;TN713

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