本文選題：SOC芯片 + AES算法　； 參考：《遼寧大學(xué)》2015年碩士論文

【摘要】：隨著信息安全變得日益重要,高級加密標準(Advanced Encryption Standard,AES)被越來越廣泛的使用。本文研究的主要目的是如何減少AES硬件實現(xiàn)的硬件消耗。本文介紹了AES算法的原理以及硬件實現(xiàn)方法,并且為了減少AES的硬件消耗,提出了一系列的優(yōu)化方法,這些方法的設(shè)計與實現(xiàn)是本文的主要工作也是主要的閃光點。其中包括:半等效解密算法,加解密資源共享,S-BOX的合成域?qū)崿F(xiàn),加解密時密鑰的實時產(chǎn)生,列混合變換的字節(jié)級設(shè)計,行變換優(yōu)化。本文通過分析直接解密算法和等效解密算法的優(yōu)缺點,最終采用半等效解密算法,最大實現(xiàn)加解密的資源共用;通過有限域的性質(zhì)以及合成域的相關(guān)知識,實現(xiàn)了用邏輯實現(xiàn)的加解密共用的S-BOX;由于現(xiàn)在大多數(shù)密鑰產(chǎn)生及使用的方法是將密鑰一次性提前擴展后存儲,以實現(xiàn)加解密共用,此方法會浪費大量的存儲資源,所以本文詳細的介紹了如何實時的去擴展并輸出每輪加解密所需的密鑰,實現(xiàn)了資源的優(yōu)化;列混合變換的加解密所需的系數(shù)差別很大,所以大多數(shù)設(shè)計會設(shè)置兩套單獨的列混合變換,本文詳細的介紹了如何在Byte級去設(shè)計列混合變換,使加解密共用一套列混合變換;另外本文通過分析行移位變換的加密與解密結(jié)果,優(yōu)化了行移位變換。通過本文介紹的優(yōu)化及設(shè)計方法,可以實現(xiàn)AES加密算法的硬件實現(xiàn)并做到顯著的優(yōu)化。其中,寄存器的數(shù)量降低到了原設(shè)計的25%,門數(shù)降低到了原設(shè)計的50%。
[Abstract]:As information security becomes more and more important, Advanced Encryption Standard AESs are becoming more and more widely used. The main purpose of this paper is to reduce the hardware consumption of AES hardware implementation. This paper introduces the principle of AES algorithm and hardware implementation method, and in order to reduce the hardware consumption of AES, a series of optimization methods are proposed. The design and implementation of these methods is the main work of this paper is also the main flash point. These include: semi-equivalent decryption algorithm, implementation of S-BOX synthesis domain, real-time generation of key during encryption and decryption, byte level design of column mixed transformation, and optimization of row transformation. By analyzing the advantages and disadvantages of the direct decryption algorithm and the equivalent decryption algorithm, this paper uses the semi-equivalent decryption algorithm to maximize the resource sharing of encryption and decryption. The S-BOX-based encryption and decryption sharing implemented by logic is implemented. Because most of the key generation and usage methods are stored in advance after the key is expanded in advance, so as to realize encryption and decryption sharing, this method will waste a lot of storage resources. Therefore, this paper introduces in detail how to extend and output the key needed for each round of encryption and decryption in real time, and realize the optimization of resources. So most design will set two separate column mixed transformation, this paper introduces how to design column mixed transform in Byte level, so that encryption and decryption share a set of column mixed transformation; In addition, by analyzing the encryption and decryption results of line shift transform, the line shift transform is optimized. Through the optimization and design method introduced in this paper, the hardware implementation of AES encryption algorithm can be realized and significant optimization can be achieved. The number of registers is reduced to 25 and the number of gates is reduced to 50.
【學(xué)位授予單位】：遼寧大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN47

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本文編號：1825934