本文選題：邏輯綜合 + 可測(cè)性設(shè)計(jì)��； 參考：《西安電子科技大學(xué)》2015年碩士論文

【摘要】：隨著科技的進(jìn)步與人們需求的不斷提高,越來(lái)越多的高科技產(chǎn)品陸續(xù)的問(wèn)世,而這些產(chǎn)品的出現(xiàn)大多數(shù)得益于集成電路技術(shù)的不斷發(fā)展與進(jìn)步。在半導(dǎo)體行業(yè)存在著一個(gè)摩爾定律,它預(yù)測(cè)芯片的集成度大概每十八個(gè)月左右就會(huì)增加一倍,規(guī)模的提高將要求工藝尺寸隨之下降。工藝尺寸不斷下降會(huì)使寄生效應(yīng)變得更加嚴(yán)重,時(shí)序收斂難度增大。考慮到由寄生效應(yīng)引起的信號(hào)完整性、動(dòng)態(tài)電壓降以及超高的集成度、GHz以上的頻率,時(shí)序收斂問(wèn)題僅僅靠工藝技術(shù)的提升是難以得到解決的。作為一名物理設(shè)計(jì)和實(shí)施工程師,其艱巨任務(wù)就是在這種條件下如何實(shí)現(xiàn)縮短芯片設(shè)計(jì)的周期,快速進(jìn)入市場(chǎng)。因此,物理設(shè)計(jì)絕對(duì)不是僅僅熟悉后端設(shè)計(jì)的整個(gè)流程和熟練掌握EDA工具就可以的,它需要工程師對(duì)于設(shè)計(jì)目標(biāo)的總體特征以及物理實(shí)現(xiàn)的方法都有充分透徹的理解。本文按照ASIC后端設(shè)計(jì)的流程,采用TSMC 0.18um 1P6M COMS工藝實(shí)現(xiàn)8位RSIC_CPU的后端設(shè)計(jì),主要設(shè)計(jì)流程及研究結(jié)果如下:1.對(duì)邏輯綜合理論的研究。邏輯綜合是將具有一定功能的RTL級(jí)代碼綜合、映射成電路結(jié)構(gòu),本文重點(diǎn)研究了邏輯綜合過(guò)程中如何對(duì)設(shè)計(jì)目標(biāo)添加時(shí)序約束和工作環(huán)境的設(shè)置,與此同時(shí),闡述了綜合時(shí)對(duì)于多時(shí)鐘域路徑的時(shí)序約束的處理方法以及邏輯綜合實(shí)現(xiàn)的過(guò)程和對(duì)于違例路徑的優(yōu)化方法�；谝陨侠碚撏瓿闪�8位RISC_CPU的時(shí)序約束的添加、工作環(huán)境的設(shè)置,實(shí)現(xiàn)了對(duì)該設(shè)計(jì)的邏輯綜合,查看綜合后的時(shí)序報(bào)告文件檢驗(yàn)時(shí)序是否收斂,對(duì)設(shè)計(jì)目標(biāo)的邏輯綜合進(jìn)行優(yōu)化生成門(mén)級(jí)網(wǎng)表。最后利用Formality基于形式驗(yàn)證的方法對(duì)該設(shè)計(jì)的邏輯綜合前后邏輯功能進(jìn)行等價(jià)性檢查,確保綜合產(chǎn)生的網(wǎng)表文件與RTL級(jí)代碼描述的邏輯功能是一致的。2.對(duì)可測(cè)性設(shè)計(jì)的研究。隨著集成電路規(guī)模的發(fā)展,測(cè)試成本所占比重越發(fā)突出,為了降低設(shè)計(jì)過(guò)程中測(cè)試所耗費(fèi)的成本,減小出現(xiàn)故障的幾率,提高設(shè)計(jì)的質(zhì)量和量產(chǎn)的成品率,可測(cè)性設(shè)計(jì)在芯片設(shè)計(jì)中得到廣泛應(yīng)用。本文介紹了可測(cè)性設(shè)計(jì)的基本理論知識(shí)和設(shè)計(jì)實(shí)踐中常用的測(cè)試方法以及常見(jiàn)的故障類(lèi)型,討論了測(cè)試的設(shè)計(jì)規(guī)則,完成了8位RISC_CPU的掃描測(cè)試和故障測(cè)試,進(jìn)行了測(cè)試覆蓋率的檢查,采用兩種不同方法對(duì)設(shè)計(jì)進(jìn)行優(yōu)化,去除了測(cè)試中引腳不可控問(wèn)題,提高測(cè)試覆蓋率。最后在設(shè)計(jì)中插入了掃描鏈完成測(cè)試并對(duì)DFT后的時(shí)序進(jìn)行分析。3.對(duì)靜態(tài)時(shí)序分析的研究。論述了靜態(tài)時(shí)序分析的基本原理,延時(shí)計(jì)算與參數(shù)提取的方法。對(duì)時(shí)序路徑進(jìn)行劃分與時(shí)序分析,檢查違例路徑。介紹了常見(jiàn)的造成時(shí)序違例的因素及時(shí)序優(yōu)化的方法。重點(diǎn)介紹了OCV條件下的時(shí)序分析以及共同路徑悲觀方法的相關(guān)內(nèi)容,本文采用基于CPPR的方法完成了8位RISC_CPU的時(shí)序分析,保證時(shí)序滿(mǎn)足時(shí)序約束的要求。4.對(duì)物理實(shí)現(xiàn)過(guò)程的研究。簡(jiǎn)述了數(shù)字后端設(shè)計(jì)的設(shè)計(jì)流程,研究了布圖規(guī)劃的內(nèi)容以及其結(jié)果對(duì)后續(xù)設(shè)計(jì)時(shí)序的相關(guān)影響。在時(shí)鐘樹(shù)綜合過(guò)程,采用了手動(dòng)與自動(dòng)相結(jié)合的方法完成了時(shí)鐘樹(shù)的綜合,減小時(shí)鐘葉節(jié)點(diǎn)之間的skew。最后,將routing后的網(wǎng)表與布圖前的網(wǎng)表通過(guò)形式驗(yàn)證完成了一致性檢查,確保物理實(shí)現(xiàn)前后設(shè)計(jì)的邏輯功能沒(méi)發(fā)生改變。
[Abstract]:With the progress of science and technology and the increasing demand of people, more and more high-tech products have come out in succession. Most of these products are due to the continuous development and progress of integrated circuit technology. There is a Moore law in the semiconductor industry, which predicts the integration of chips will increase about every eighteen months. The increase in scale will require a decrease in the size of the process. The continuous decline in the process size makes the parasitic effect more serious and the time series converges more difficult. Considering the signal integrity, dynamic voltage drop, and ultra high integration, the frequency of GHz above the frequency of the parasitism, the problem of time series convergence is only dependent on the improvement of technology technology. It is difficult to solve the problem. As a physical design and Implementation Engineer, the difficult task is how to shorten the cycle of chip design under this condition and quickly enter the market. Therefore, the physical design is absolutely not only familiar with the whole process of the back end design and the skillful mastery of the EDA tool. It requires engineers to set up the design. The overall characteristics of the target and the method of physical realization are fully understood. According to the process of the ASIC backend design, this paper uses the TSMC 0.18um 1P6M COMS process to realize the back end design of 8 bit RSIC_CPU. The main design process and the results are as follows: 1. the study of the logic synthesis theory. Logic synthesis is a RTL with a certain function. The level code is integrated and mapped into the circuit structure. This paper focuses on how to add the timing constraints and the setting of work environment to the design target in the logic synthesis process. At the same time, the process of dealing with the time sequence constraints of the multi clock domain path, the process of logical synthesis and the optimization method for the violation path are expounded. Based on the above theory, the time sequence constraints of the 8 bit RISC_CPU are added, and the setting of the working environment has realized the logical synthesis of the design. The test sequence of the time series report files after the synthesis is convergent, and the logic synthesis of the design target is optimized to generate the gate level net table. Finally, the method based on the formal verification of Formality is used. The logic function of the integrated logic integrated before and after the design is checked to ensure that the integrated network table file and the logic function of the RTL level code description are the same.2. for the measurable design. With the development of the integrated circuit scale, the proportion of the test cost is more prominent, and the cost of reducing the test in the design process is reduced and the cost is reduced. The probability of small failure, improving the quality of design and yield of product, is widely used in the design of chip. This paper introduces the basic theory of testability design, the common test methods and common fault types in the design practice, and discusses the design rules of the test and completes the 8 bit RISC_CPU scan. Test and fault test, test coverage rate, use two different methods to optimize the design, remove the pin uncontrollable problem in the test, improve the test coverage. Finally, in the design, the scan chain is inserted to complete the test and the time sequence analysis after DFT is analyzed. The static time sequence analysis is discussed. The static time is discussed. The basic principle of sequence analysis, the method of time delay calculation and parameter extraction. The time sequence path is divided and time series analysis, and the violation path is checked. The method of time sequence optimization is introduced. The time sequence analysis and the related content of the common path pessimistic method are introduced. The base of this paper is based on the OCV condition. In the method of CPPR, the time sequence analysis of 8 bit RISC_CPU is completed to ensure that the time sequence satisfies the requirement of time series constraints and the study of the physical realization process. The design process of the digital back end design is introduced, the content of the layout planning and the related effects on the sequence of the subsequent design are studied. The manual and self use are adopted in the clock tree synthesis process. The combination of moving phase completes the synthesis of clock tree, reduces the skew. between hourly clock and leaf nodes, and completes the consistency check by verifying the net table after routing and the network table before the layout, ensuring that the logic function of the design before and after the physical implementation has not changed.

【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN402

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本文編號(hào)：1821157