本文選題：邏輯綜合 + 可測性設計��； 參考：《西安電子科技大學》2015年碩士論文

【摘要】：隨著科技的進步與人們需求的不斷提高,越來越多的高科技產品陸續(xù)的問世,而這些產品的出現(xiàn)大多數得益于集成電路技術的不斷發(fā)展與進步。在半導體行業(yè)存在著一個摩爾定律,它預測芯片的集成度大概每十八個月左右就會增加一倍,規(guī)模的提高將要求工藝尺寸隨之下降。工藝尺寸不斷下降會使寄生效應變得更加嚴重,時序收斂難度增大�？紤]到由寄生效應引起的信號完整性、動態(tài)電壓降以及超高的集成度、GHz以上的頻率,時序收斂問題僅僅靠工藝技術的提升是難以得到解決的。作為一名物理設計和實施工程師,其艱巨任務就是在這種條件下如何實現(xiàn)縮短芯片設計的周期,快速進入市場。因此,物理設計絕對不是僅僅熟悉后端設計的整個流程和熟練掌握EDA工具就可以的,它需要工程師對于設計目標的總體特征以及物理實現(xiàn)的方法都有充分透徹的理解。本文按照ASIC后端設計的流程,采用TSMC 0.18um 1P6M COMS工藝實現(xiàn)8位RSIC_CPU的后端設計,主要設計流程及研究結果如下:1.對邏輯綜合理論的研究。邏輯綜合是將具有一定功能的RTL級代碼綜合、映射成電路結構,本文重點研究了邏輯綜合過程中如何對設計目標添加時序約束和工作環(huán)境的設置,與此同時,闡述了綜合時對于多時鐘域路徑的時序約束的處理方法以及邏輯綜合實現(xiàn)的過程和對于違例路徑的優(yōu)化方法�；谝陨侠碚撏瓿闪�8位RISC_CPU的時序約束的添加、工作環(huán)境的設置,實現(xiàn)了對該設計的邏輯綜合,查看綜合后的時序報告文件檢驗時序是否收斂,對設計目標的邏輯綜合進行優(yōu)化生成門級網表。最后利用Formality基于形式驗證的方法對該設計的邏輯綜合前后邏輯功能進行等價性檢查,確保綜合產生的網表文件與RTL級代碼描述的邏輯功能是一致的。2.對可測性設計的研究。隨著集成電路規(guī)模的發(fā)展,測試成本所占比重越發(fā)突出,為了降低設計過程中測試所耗費的成本,減小出現(xiàn)故障的幾率,提高設計的質量和量產的成品率,可測性設計在芯片設計中得到廣泛應用。本文介紹了可測性設計的基本理論知識和設計實踐中常用的測試方法以及常見的故障類型,討論了測試的設計規(guī)則,完成了8位RISC_CPU的掃描測試和故障測試,進行了測試覆蓋率的檢查,采用兩種不同方法對設計進行優(yōu)化,去除了測試中引腳不可控問題,提高測試覆蓋率。最后在設計中插入了掃描鏈完成測試并對DFT后的時序進行分析。3.對靜態(tài)時序分析的研究。論述了靜態(tài)時序分析的基本原理,延時計算與參數提取的方法。對時序路徑進行劃分與時序分析,檢查違例路徑。介紹了常見的造成時序違例的因素及時序優(yōu)化的方法。重點介紹了OCV條件下的時序分析以及共同路徑悲觀方法的相關內容,本文采用基于CPPR的方法完成了8位RISC_CPU的時序分析,保證時序滿足時序約束的要求。4.對物理實現(xiàn)過程的研究。簡述了數字后端設計的設計流程,研究了布圖規(guī)劃的內容以及其結果對后續(xù)設計時序的相關影響。在時鐘樹綜合過程,采用了手動與自動相結合的方法完成了時鐘樹的綜合,減小時鐘葉節(jié)點之間的skew。最后,將routing后的網表與布圖前的網表通過形式驗證完成了一致性檢查,確保物理實現(xiàn)前后設計的邏輯功能沒發(fā)生改變。
[Abstract]:With the progress of science and technology and the increasing demand of people, more and more high-tech products have come out in succession. Most of these products are due to the continuous development and progress of integrated circuit technology. There is a Moore law in the semiconductor industry, which predicts the integration of chips will increase about every eighteen months. The increase in scale will require a decrease in the size of the process. The continuous decline in the process size makes the parasitic effect more serious and the time series converges more difficult. Considering the signal integrity, dynamic voltage drop, and ultra high integration, the frequency of GHz above the frequency of the parasitism, the problem of time series convergence is only dependent on the improvement of technology technology. It is difficult to solve the problem. As a physical design and Implementation Engineer, the difficult task is how to shorten the cycle of chip design under this condition and quickly enter the market. Therefore, the physical design is absolutely not only familiar with the whole process of the back end design and the skillful mastery of the EDA tool. It requires engineers to set up the design. The overall characteristics of the target and the method of physical realization are fully understood. According to the process of the ASIC backend design, this paper uses the TSMC 0.18um 1P6M COMS process to realize the back end design of 8 bit RSIC_CPU. The main design process and the results are as follows: 1. the study of the logic synthesis theory. Logic synthesis is a RTL with a certain function. The level code is integrated and mapped into the circuit structure. This paper focuses on how to add the timing constraints and the setting of work environment to the design target in the logic synthesis process. At the same time, the process of dealing with the time sequence constraints of the multi clock domain path, the process of logical synthesis and the optimization method for the violation path are expounded. Based on the above theory, the time sequence constraints of the 8 bit RISC_CPU are added, and the setting of the working environment has realized the logical synthesis of the design. The test sequence of the time series report files after the synthesis is convergent, and the logic synthesis of the design target is optimized to generate the gate level net table. Finally, the method based on the formal verification of Formality is used. The logic function of the integrated logic integrated before and after the design is checked to ensure that the integrated network table file and the logic function of the RTL level code description are the same.2. for the measurable design. With the development of the integrated circuit scale, the proportion of the test cost is more prominent, and the cost of reducing the test in the design process is reduced and the cost is reduced. The probability of small failure, improving the quality of design and yield of product, is widely used in the design of chip. This paper introduces the basic theory of testability design, the common test methods and common fault types in the design practice, and discusses the design rules of the test and completes the 8 bit RISC_CPU scan. Test and fault test, test coverage rate, use two different methods to optimize the design, remove the pin uncontrollable problem in the test, improve the test coverage. Finally, in the design, the scan chain is inserted to complete the test and the time sequence analysis after DFT is analyzed. The static time sequence analysis is discussed. The static time is discussed. The basic principle of sequence analysis, the method of time delay calculation and parameter extraction. The time sequence path is divided and time series analysis, and the violation path is checked. The method of time sequence optimization is introduced. The time sequence analysis and the related content of the common path pessimistic method are introduced. The base of this paper is based on the OCV condition. In the method of CPPR, the time sequence analysis of 8 bit RISC_CPU is completed to ensure that the time sequence satisfies the requirement of time series constraints and the study of the physical realization process. The design process of the digital back end design is introduced, the content of the layout planning and the related effects on the sequence of the subsequent design are studied. The manual and self use are adopted in the clock tree synthesis process. The combination of moving phase completes the synthesis of clock tree, reduces the skew. between hourly clock and leaf nodes, and completes the consistency check by verifying the net table after routing and the network table before the layout, ensuring that the logic function of the design before and after the physical implementation has not changed.

【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN402

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本文編號：1821157