本文選題：SerDes + 信道衰減　； 參考：《國防科學(xué)技術(shù)大學(xué)》2015年碩士論文

【摘要】：隨著通信技術(shù)的不斷提升,數(shù)據(jù)傳輸量大大提高,為了在盡量短的時間內(nèi)傳遞更多的信息,需要大幅度提升傳輸速率。當(dāng)數(shù)據(jù)傳輸速率達(dá)到Gbps以上之后,傳輸線上的衰減加劇,數(shù)據(jù)間的干擾更加嚴(yán)重,誤碼率不斷提高。傳統(tǒng)的并行數(shù)據(jù)已不能滿足高速數(shù)據(jù)之間的傳輸?shù)男枨?但是新型串行鏈路傳輸方式卻能滿足這種高速傳輸?shù)男枨蟆erDes作為一種典型的串行數(shù)據(jù)傳輸方式,其研究越來越得到重視。本文基于65nm工藝,在研究SerDes發(fā)送器的理論基礎(chǔ)上設(shè)計了一款速率能夠達(dá)到6.25Gbps的Ser Des發(fā)送器。該發(fā)送器的輸入為20位的并行數(shù)據(jù),輸出為一對差分的數(shù)據(jù),輸出數(shù)據(jù)帶有0-9.6dB可編程預(yù)加重功能。本文的主要工作分為以下幾點:1)分析比較三種并串轉(zhuǎn)換電路結(jié)構(gòu)的優(yōu)缺點,結(jié)合本文設(shè)計發(fā)送器需要滿足的傳輸速率,設(shè)計了在低速情況下使用移位寄存器型并串轉(zhuǎn)換結(jié)構(gòu)和在高速情況下使用CML結(jié)構(gòu)的并串轉(zhuǎn)換電路;2)設(shè)計并實現(xiàn)了占空比調(diào)節(jié)電路保證在整個并串轉(zhuǎn)換過程中使用的時鐘的占空比為50%;3)設(shè)計并實現(xiàn)了可編程預(yù)加重驅(qū)動器,最大能夠彌補(bǔ)9.6dB的信道損耗,能夠有效的消弱前標(biāo)和后標(biāo)碼間干擾;4)設(shè)計接收端檢測電路來檢測接收端是否存在;本文設(shè)計了SerDes發(fā)送器的電路、版圖,對設(shè)計的電路和版圖做了詳盡的仿真,得到仿真結(jié)果完全滿足PCIE2.0的協(xié)議要求。發(fā)送器輸出的數(shù)據(jù)速率能夠達(dá)到6.25Gbps、5Gbps、3.125Gbps、2.5Gbps和1.25Gbps;輸出數(shù)據(jù)幅值能夠?qū)崿F(xiàn)0.8-1.2V可調(diào);輸出數(shù)據(jù)眼圖的眼高滿足要求,左右張開能夠達(dá)到0.9UI;jitter小于0.1UI。
[Abstract]:With the continuous improvement of communication technology, the amount of data transmission is greatly increased, in order to transfer more information in as short a time as possible, it is necessary to greatly improve the transmission rate. When the data transmission rate reaches above Gbps, the attenuation on the transmission line increases, the interference between the data becomes more serious, and the bit error rate increases continuously. The traditional parallel data can not meet the needs of high-speed data transmission, but the new serial link transmission mode can meet the demand of high-speed transmission. SerDes is a typical serial data transmission mode. More and more attention has been paid to its research. Based on the 65nm process, a Ser Des transmitter with the rate of 6.25Gbps is designed on the basis of studying the theory of SerDes transmitter. The input of the transmitter is 20 bit parallel data, the output data is a pair of difference data, the output data has 0-9.6dB programmable preweighting function. The main work of this paper is divided into the following points: 1) analyzing and comparing the advantages and disadvantages of the three parallel series conversion circuit structures, combining with the design of the transmitter in this paper to meet the transmission rate. In this paper, we design and implement the shift register type parallel string conversion circuit at low speed and the parallel string conversion circuit with CML structure at high speed. (2) the duty cycle adjusting circuit is designed and implemented to ensure the use of the circuit in the whole process of parallel string conversion. Designed and implemented a programmable pre-emphasis driver The maximum can compensate for the channel loss of 9.6dB, and can effectively reduce the pre-standard and post-code inter-symbol interference (4) the design of the receiver detection circuit to detect the existence of the receiver; this paper designed the SerDes transmitter circuit, layout, The designed circuit and layout are simulated in detail, and the simulation results fully meet the requirements of PCIE2.0 protocol. The output data rate of the transmitter can reach 6.25Gbps-5Gbps-3.125Gbps-2.5Gbps and 1.25Gbps.The output data amplitude can be adjusted 0.8-1.2V, and the eye height of the output data can meet the requirements, and the left and right opening can reach 0.9U Ijitter less than 0.1UI.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN402

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本文編號：1820555