本文選題：超高速 + 采樣保持電路��； 參考：《合肥工業(yè)大學(xué)》2017年碩士論文

【摘要】：模數(shù)轉(zhuǎn)換器(Analog-to-Digital Converter,ADC)作為模擬信號向數(shù)字信號轉(zhuǎn)換的關(guān)鍵電路,廣泛應(yīng)用于現(xiàn)代通信、圖像采集、醫(yī)療電子等眾多領(lǐng)域。隨著軟件無線電和通信高頻化的發(fā)展,ADC也朝著高速方向發(fā)展,因此超高速ADC的研究受到學(xué)術(shù)界的廣泛關(guān)注。采樣保持電路(Trcak and Hold Circuit,THC)位于超高速ADC的最前端,是十分重要的組成部分,其作用是將連續(xù)變化的模擬輸入信號的瞬時值通過采樣和保持轉(zhuǎn)換為離散信號,并保持一段時間供后級核心電路進行量化和編碼。因為THC位于ADC的最前端,因此其性能直接影響整個ADC的性能。如何在保證精度的情況下,盡可能提高THC采樣速率是研究的關(guān)鍵。本文基于設(shè)計高速高精度折疊插值A(chǔ)DC的背景,選擇開環(huán)架構(gòu)來設(shè)計超高速THC,并針對開環(huán)THC架構(gòu)的優(yōu)缺點,研究影響速度和精度的關(guān)鍵點;分析非線性對電路性能的影響,并通過引入帶有源極退化技術(shù)的級間緩沖器、高線性度的柵壓自舉開關(guān)以及虛擬開關(guān)吸收電荷注入等技術(shù)來提高THC的線性度;采用兩通道時間交織架構(gòu)提高THC的采樣速率,并且針對兩通道的失調(diào)失配,使用手動校準失調(diào)補償技術(shù)來減小誤差;采用全深N阱管的差分運放結(jié)構(gòu)作為緩沖器;此外,還設(shè)計了供電模塊給級間緩沖器供電以及電荷泵復(fù)位減小捕獲時間。本文在Cadence Spectre環(huán)境下基于TSMC 0.18μm CMOS工藝設(shè)計和仿真電路,采用2V單電源供電。整體電路仿真結(jié)果表明,在1GSps的采樣率下,采用相干采樣,負載電容為預(yù)放大器寄生電容,輸入800mVpp的正弦波,信號與噪聲失真比(SNDR)達到 75.56dB,有效位數(shù)(ENOB)超過 12.25 位,達到了 12 位 1GSps ADC對于前端THC的性能要求。
[Abstract]:As the key circuit of analog to digital signal conversion, Analog-to-Digital converter (ADC) is widely used in many fields such as modern communication, image acquisition, medical electronics and so on. With the development of high frequency software radio and communication, the research of ultra high speed ADC has been paid more and more attention. Trcak and Hold circuit is a very important component of ultra-high speed ADC, which is used to convert the instantaneous value of continuously changing analog input signal into discrete signal by sampling and holding. And maintain a period of time for the core circuit after the quantization and coding. Because THC is at the front end of ADC, its performance directly affects the performance of the entire ADC. How to improve the sampling rate of THC as much as possible under the condition of ensuring precision is the key to the research. Based on the background of designing high speed and high precision foldable interpolated ADC, open loop architecture is chosen to design ultra high speed THC, and the key points that affect speed and precision are studied according to the advantages and disadvantages of open loop THC architecture, and the influence of nonlinearity on circuit performance is analyzed. The linearity of THC is improved by introducing interstage buffer with source pole degradation technology, high linearity gate voltage bootstrap switch and virtual switch absorption charge injection, and using two channel time interleaving architecture to improve the sampling rate of THC. Aiming at the mismatch of the two channels, the manual calibration offset compensation technique is used to reduce the error; the differential operational amplifier structure of the all-deep N-well tube is used as the buffer; in addition, The power supply module is designed to supply the interstage buffer and the charge pump reset to reduce the capture time. In this paper, based on TSMC 0.18 渭 m CMOS process design and simulation circuit in Cadence Spectre environment, 2V single power supply is used. The simulation results of the whole circuit show that under the sampling rate of 1GSps, the coherent sampling is used, the load capacitance is the parasitic capacitance of preamplifier, the sinusoidal wave of the input 800mVpp is input, the ratio of signal to noise distortion is 75.56 dB, and the effective bit ENOB is more than 12.25 bits. The performance requirements of 12 bit 1GSps ADC for front end THC are achieved.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN792

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本文編號：1810591