本文選題：漏功耗 + 標(biāo)準(zhǔn)單元包　； 參考：《寧波大學(xué)》2015年碩士論文

【摘要】：隨著集成電路的迅速發(fā)展,CMOS超大規(guī)模集成電路(VLSI)設(shè)計(jì)工藝已進(jìn)入納米尺度,納米MOS器件閾值電壓的縮小使得芯片的漏電流呈指數(shù)形式增加,從而造成芯片漏功耗的迅速增大,漏功耗已成為芯片總功耗中不可忽略的組成部分。標(biāo)準(zhǔn)單元在數(shù)字ASIC集成電路設(shè)計(jì)中的作用非常重要,減小標(biāo)準(zhǔn)單元的功耗將會(huì)使ASIC芯片的總功耗降低。在納米工藝下,降低標(biāo)準(zhǔn)單元的漏功耗將直接影響ASIC芯片漏功耗水平。因此研究低漏功耗標(biāo)準(zhǔn)單元對(duì)低漏功耗ASIC芯片的設(shè)計(jì)有著非常重要的意義。本文介紹了CMOS電路的漏功耗降低技術(shù)和標(biāo)準(zhǔn)單元建庫技術(shù)的相關(guān)知識(shí)背景。在NCSU 45nm工藝下,開展標(biāo)準(zhǔn)單元低漏功耗技術(shù)的研究,構(gòu)建了一個(gè)低漏功耗標(biāo)準(zhǔn)單元包,為基于標(biāo)準(zhǔn)單元的低漏功耗ASIC設(shè)計(jì)提供了基礎(chǔ)。本課題的研究分為以下幾個(gè)部分:1、研究納米工藝下漏功耗減小技術(shù),并應(yīng)用于標(biāo)準(zhǔn)單元設(shè)計(jì)中。采用溝長調(diào)制技術(shù)對(duì)NCSU 45nm工藝的標(biāo)準(zhǔn)單元進(jìn)行分析,并對(duì)標(biāo)準(zhǔn)單元的晶體管尺寸進(jìn)行優(yōu)化,以期達(dá)到減小漏功耗的目的;根據(jù)優(yōu)化的晶體管尺寸進(jìn)行了常用標(biāo)準(zhǔn)單元的低漏功耗設(shè)計(jì),主要包括常用組合邏輯門電路和觸發(fā)器等標(biāo)準(zhǔn)單元;基于功控休眠技術(shù)提出了一種新的具有數(shù)據(jù)保持功能的低漏功耗主從D觸發(fā)器結(jié)構(gòu);2、對(duì)低漏功耗標(biāo)準(zhǔn)單元進(jìn)行版圖庫的設(shè)計(jì)。繪制低漏功耗標(biāo)準(zhǔn)單元的版圖,然后采用Virtuoso IC610自帶的Stream Out導(dǎo)出版圖庫文件(GDS文件),并做了DRC、LVS等規(guī)則檢查,完成版圖庫的設(shè)計(jì)。繪制低漏功耗單元的版圖時(shí),應(yīng)嚴(yán)格遵照NCSU 45nm的工藝文件規(guī)則,以減少布局布線階段的布線誤差。例如,標(biāo)準(zhǔn)單元的高度要相同,高度寬度都要是金屬與金屬之間的最小間距(pitch)的整數(shù)倍,PIN要擺放在水平和垂直的布線通道的交匯處等等;3、對(duì)低漏功耗標(biāo)準(zhǔn)單元進(jìn)行物理庫和時(shí)序綜合庫的設(shè)計(jì)。使用Cadence公司的Abstract工具提取標(biāo)準(zhǔn)單元的物理抽象,包括金屬層的距離和形狀,PIN的位置等信息的提取,生成物理庫。使用Liberty NCX和HSPICE實(shí)現(xiàn)標(biāo)準(zhǔn)單元的特征化,生成可邏輯綜合的時(shí)序綜合庫;4、對(duì)低漏功耗標(biāo)準(zhǔn)單元包進(jìn)行驗(yàn)證。利用所設(shè)計(jì)的低漏功耗CMOS標(biāo)準(zhǔn)單元包進(jìn)行加法器和FIR濾波器的設(shè)計(jì);完成了從邏輯綜合到布局布線的后端設(shè)計(jì),對(duì)所設(shè)計(jì)的低漏功耗CMOS標(biāo)準(zhǔn)單元包進(jìn)行可用性和有效性驗(yàn)證。結(jié)果表明,本文所設(shè)計(jì)的低漏功耗CMOS標(biāo)準(zhǔn)單元包可以被主流的EDA工具調(diào)用,同時(shí)該低漏功耗CMOS標(biāo)準(zhǔn)單元包降低了電路的漏功耗,與NCSU 45nm標(biāo)準(zhǔn)單元庫相比,4位串行加法器電路的漏功耗降低了9.50%,16階FIR數(shù)字濾波器的漏功耗降低16.77%。另外FIR數(shù)字濾波器的電路面積也得到了3.27%的優(yōu)化。
[Abstract]:With the rapid development of integrated circuits, the design process of VLSI has entered the nanometer scale. The decrease of threshold voltage of MOS devices makes the leakage current of the chip increase exponentially, resulting in the rapid increase of leakage power consumption. Leakage power has become an important part of the total power consumption. The function of standard cell in the design of digital ASIC integrated circuit is very important. Reducing the power consumption of standard cell will reduce the total power consumption of ASIC chip. In nanotechnology, reducing the leakage power of standard cells will directly affect the leakage power level of ASIC chips. Therefore, it is very important to study the low leakage power standard cell for the design of low leakage power ASIC chip. This paper introduces the leakage power reduction technology of CMOS circuit and the knowledge background of standard cell library building technology. In the NCSU 45nm process, a low leakage power standard cell package is constructed, which provides the basis for the design of low leakage power ASIC based on standard cell. The research of this paper is divided into the following parts: 1. The leakage power reduction technology under nanotechnology is studied and applied to the design of standard cell. The standard cell of NCSU 45nm process is analyzed by channel length modulation technique, and the transistor size of standard cell is optimized in order to reduce leakage power consumption. According to the optimized transistor size, the low leakage power design of common standard cells is carried out, which mainly includes standard cells such as combinatorial logic gates and flip-flop. Based on power control sleep technology, a new low leakage power master-slave D flip-flop structure with data retention function is proposed. The layout of low leakage power standard cell is drawn, and then the layout library file is exported by Stream Out of Virtuoso IC610, and the rule checking is done to complete the design of plate library. When drawing the layout of low leakage power unit, we should strictly follow the rules of NCSU 45nm process file, so as to reduce the routing error in layout and routing stage. For example, the height of a standard cell is the same, The height and width should be the minimum distance between metal and metal. The PIN should be placed at the intersection of horizontal and vertical wiring channels and so on. The physical library and time sequence synthesis library of low leakage power standard cell are designed. The physical abstraction of the standard unit is extracted by using Cadence's Abstract tools, including the extraction of the distance of metal layer and the position of the shape of the PIN, and the physical library is generated. Liberty NCX and HSPICE are used to realize the feature of the standard cell, and the logical synthesis time sequence synthesis library is generated, and the low leakage power standard cell package is verified. The low leakage power CMOS standard cell packet is used to design the adder and FIR filter, the back-end design from logic synthesis to layout and routing is completed, and the usability and validity of the designed CMOS standard cell package are verified. The results show that the low leakage power CMOS standard cell package designed in this paper can be called by the mainstream EDA tools, and the low leakage power CMOS standard cell packet can reduce the leakage power of the circuit. Compared with the NCSU 45nm standard cell library, the leakage power consumption of the 4-bit serial adder circuit is reduced by 16.777.The leakage power consumption of the 16-order FIR digital filter is reduced by 9.50th order. In addition, the circuit area of FIR digital filter is optimized by 3.27%.
【學(xué)位授予單位】：寧波大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN432

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 羅靜;陶建中;;0．5μm CMOS標(biāo)準(zhǔn)單元庫建庫流程技術(shù)研究[J];電子與封裝;2006年01期

，

本文編號(hào)：1793825