本文選題：漏電流 + 漏功耗　； 參考：《寧波大學(xué)》2015年碩士論文

【摘要】：隨著集成電路的發(fā)展,集成電路的規(guī)模越來越大,集成度越來越高,大規(guī)模集成電路的性能決定著電子設(shè)備的性能。目前,移動終端電子設(shè)備對于集成電路芯片的性能要求越來越嚴(yán)格,伴隨著工藝制程的進(jìn)步,漏電流的種類越來越多,漏功耗占電路總功耗的比重越來越大,因此高速低功耗集成電路芯片的設(shè)計已經(jīng)成為集成電路行業(yè)發(fā)展的必然趨勢。加法運(yùn)算是在數(shù)字電子系統(tǒng)中最基本的算術(shù)邏輯運(yùn)算,加法器是數(shù)字系統(tǒng)中最基本的邏輯運(yùn)算單元,它常常應(yīng)用于多位加法器的進(jìn)位關(guān)鍵路徑中,是影響電子設(shè)備性能的重要因素之一。本文列舉了多種常用加法器,通過對串行進(jìn)位加法器、線性進(jìn)位選擇加法器、超前進(jìn)位加法器、曼徹斯特加法器等的研究,分析了其基本原理以及進(jìn)位關(guān)鍵路徑的邏輯翻轉(zhuǎn)。本學(xué)位論文通過對傳統(tǒng)的低功耗CMOS集成電路加法器進(jìn)行認(rèn)真研究,總結(jié)了傳統(tǒng)加法器的優(yōu)缺點(diǎn),在此基礎(chǔ)上,通過優(yōu)化算法和改進(jìn)電路拓?fù)浣Y(jié)構(gòu),分別設(shè)計了新型4位超前進(jìn)位加法器和新型4位柵壓自舉加法器。對電路圖在SMIC130nm工藝、四種不同輸入頻率、不同負(fù)載條件下用HSPICE進(jìn)行電路仿真,以速度、功耗、功耗延時積為性能指標(biāo),分別對電路進(jìn)行綜合對比和分析。仿真結(jié)果表明新型超前進(jìn)位加法器的功耗延時積相比于串行進(jìn)位加法器和傳統(tǒng)超前進(jìn)位加法器分別減小了70%-72%和64%-66%;新型柵壓自舉加法器的功耗延時積相比于其他類型的4位加法器減小了5%-45%。通過實(shí)驗(yàn)數(shù)據(jù),進(jìn)一步證明了新型超前進(jìn)位加法器和新型柵壓自舉加法器的優(yōu)良性能,為集成電路設(shè)計者提供了一個可靠的選擇。
[Abstract]:With the development of integrated circuits, the scale of integrated circuits becomes larger and larger and the level of integration becomes higher and higher. The performance of large-scale integrated circuits determines the performance of electronic devices. At present, the performance requirements of mobile terminal electronic devices for IC chips are more and more stringent. With the progress of the process, there are more and more kinds of leakage current, and the proportion of leakage power to the total power consumption of the circuit is increasing. Therefore, the design of high-speed and low-power IC chips has become an inevitable trend in the development of integrated circuit industry. Addition is the most basic arithmetic and logic operation in the digital electronic system. The adder is the most basic logic operation unit in the digital system. It is often used in the carry-critical path of the multi-bit adder. It is one of the important factors that affect the performance of electronic equipment. This paper enumerates many kinds of commonly used adder, through the research of serial carry adder, linear carry selection adder, lead carry adder, Manchester adder and so on, analyzes its basic principle and the logical flip of the carry-critical path. In this dissertation, the advantages and disadvantages of the traditional low power CMOS integrated circuit adder are summarized. On the basis of this, the circuit topology is optimized and the circuit topology is improved. A new 4-bit carry adder and a new 4-bit gate voltage bootstrap adder are designed respectively. The circuit is simulated by HSPICE in SMIC130nm process with four different input frequencies and different loads. The circuit is compared and analyzed with the performance index of speed, power consumption and power delay product. The simulation results show that compared with serial carry adder and traditional carry adder, the power delay product of the novel advanced carry-adder is reduced by 70-72% and 64-66, respectively, and the power delay product of the new type of gate voltage bootstrap adder is lower than that of other categories. The 4-bit adder reduces the number by 5-45. Through the experimental data, the excellent performance of the new advanced carry adder and the new gate voltage bootstrap adder is further proved, which provides a reliable choice for the IC designers.
【學(xué)位授予單位】：寧波大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN791

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本文編號：1792208