發(fā)布時間：2018-04-22 12:50

  本文選題：集成電路測試 + 測試生成　； 參考：《儀器儀表學報》2016年05期

【摘要】：為應對數(shù)據(jù)通道測試中向量生成計算復雜度的日益增長,針對加法器進行研究,提出了一種基于分治策略的加法器測試向量生成技術。首先將被測加法器電路分解為并發(fā)模塊和順序模塊,分別生成對應這些模塊故障全覆蓋的測試向量子集,再將他們的輸入信號映射為被測加法器電路的基本輸入,經(jīng)去除冗余向量后得到完整的測試向量集。給出的實驗結果表明了該技術能有效地降低加法器測試向量生成的計算量,特別對于大規(guī)模加法器電路的測試生成,其效果更佳。
[Abstract]:In order to cope with the increasing computational complexity of vector generation in data channel testing, a test vector generation technique for adder based on divide-and-conquer strategy is proposed. First, the circuit of the tested adder is decomposed into concurrent modules and sequential modules, and the test vector subsets corresponding to the full fault coverage of these modules are generated, and then their input signals are mapped to the basic inputs of the adders circuit under test. After removing redundant vectors, the complete set of test vectors is obtained. The experimental results show that the proposed technique can effectively reduce the computational complexity of the test vector generation of the adder, especially for the test generation of the large-scale adder circuit.
【作者單位】： 同濟大學電子與信息工程學院;
【分類號】：TN707

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本文編號：1787288