本文選題：數(shù)模轉(zhuǎn)換器 + 電流舵結(jié)構(gòu)��； 參考：《北方工業(yè)大學(xué)》2017年碩士論文

【摘要】：在這個(gè)信息快速傳播的時(shí)代,由于在信號(hào)傳播過程中對(duì)信號(hào)傳輸時(shí)傳輸速度/精度要求越來越高,為順應(yīng)這一發(fā)展趨勢(shì)本文設(shè)計(jì)了精度為14-bit采樣率500MHz的電流舵結(jié)構(gòu)DAC。為了盡量降低一些非理想因素引起的偏差對(duì)動(dòng)態(tài)性能的影響我們采用了一種隨機(jī)選取校準(zhǔn)算法來對(duì)bit10-bit14位電流源進(jìn)行校準(zhǔn)。本文采用中芯國際SMIC0.18um標(biāo)準(zhǔn)CMOS工藝進(jìn)行設(shè)計(jì),最終完成了一款帶有數(shù)字校準(zhǔn)的DAC設(shè)計(jì)并完成了以下主要任務(wù)和創(chuàng)新:(1)對(duì)輸入信號(hào)采用bit1-bit5、bit6-bit9、bit10-bit14進(jìn)行分段,然后對(duì)bit1-bit5 二進(jìn)制譯碼,bit6-bit9、bit10-bit14 溫度計(jì)譯碼。(2)在開關(guān)控制信號(hào)傳輸進(jìn)入控制開關(guān)之前我們使用了限幅電路設(shè)計(jì),通過該設(shè)計(jì)可以有效地降低信號(hào)交叉點(diǎn)與控制信號(hào)中的非理想信號(hào)的幅度從而降低輸出信號(hào)中的毛刺。(3)對(duì)于bit10-bit14的電流源我們使用基于"數(shù)據(jù)比較"和"序列檢測(cè)"隨機(jī)選取算法對(duì)其進(jìn)行數(shù)字校準(zhǔn)。(4)在數(shù)字校準(zhǔn)單元中,通過Verilog對(duì)算法進(jìn)行功能實(shí)現(xiàn)、邏輯綜合與物理層后端版圖實(shí)現(xiàn)。在輸入信號(hào)為1MHz采樣頻率為500MHz時(shí),分別對(duì)不加校準(zhǔn)和添加校準(zhǔn)電路進(jìn)行仿真,不加校準(zhǔn)時(shí)SFDR為74.3634dB添加校準(zhǔn)之后提高到78.2798dB。由仿真結(jié)果可以看出通過數(shù)字校準(zhǔn)設(shè)計(jì)數(shù)模轉(zhuǎn)換器動(dòng)態(tài)特性得到顯著提高。
[Abstract]:In this era of rapid information transmission, the speed / precision of signal transmission is becoming more and more high in the process of signal transmission. In order to comply with this trend, a current rudder structure with precision of 14-bit sampling rate 500MHz is designed in this paper.In order to minimize the influence of the deviation caused by some non-ideal factors on the dynamic performance, a random selection calibration algorithm is used to calibrate the bit10-bit14 potential current source.In this paper, the SMIC SMIC0.18um standard CMOS process is used to design a DAC with digital calibration, and the following main tasks and innovations are accomplished. The input signal is segmented with bit1-bit5bit6-bit6-bit10-bit14, and the input signal is divided into two parts: bit1-bit5, bit6-bit6-bit10-bit14, bit1-bit5bit6-bit6-bit10-bit14.Then we use the limiting circuit design to decode bit1-bit5 binary code bit6-bit9bit10-bit14 thermometer. 2) before the switch control signal transmissions into the control switch,This design can effectively reduce the amplitude of the signal intersection and the non-ideal signal in the control signal, thus reducing the burr in the output signal.) for the current source of bit10-bit14, we use "data comparison" and "sequence detection" for the current source of bit10-bit14."A random selection algorithm is used for digital calibration. 4) in the digital calibration unit,The algorithm is implemented by Verilog, logic synthesis and physical layer back-end layout.When the input signal is 1MHz sampling frequency of 500MHz, the uncalibrated and added calibration circuits are simulated respectively. When the input signal is uncalibrated, the SFDR adds calibration to 74.3634dB and increases to 78.2798 dB.The simulation results show that the dynamic characteristics of the digital-to-analog converter are greatly improved by digital calibration.
【學(xué)位授予單位】：北方工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN792

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本文編號(hào)：1774103