本文選題：時(shí)鐘數(shù)據(jù)恢復(fù) + LVDS��； 參考：《電子科技大學(xué)》2017年碩士論文

【摘要】：隨著高速串行通信系統(tǒng)的急速發(fā)展,對(duì)數(shù)據(jù)進(jìn)行正確、高效地接收及恢復(fù)變得極為重要。過采樣型時(shí)鐘數(shù)據(jù)恢復(fù)電路具有結(jié)構(gòu)簡(jiǎn)單、功耗較低的特點(diǎn),隨著工藝尺寸的減小,過采樣型時(shí)鐘數(shù)據(jù)恢復(fù)電路相對(duì)于其他時(shí)鐘數(shù)據(jù)恢復(fù)電路結(jié)構(gòu),如被廣泛應(yīng)用的基于PLL型結(jié)構(gòu)逐漸顯示出兩大優(yōu)勢(shì):(1)過采樣型時(shí)鐘數(shù)據(jù)恢復(fù)電路無時(shí)鐘相位反饋回路,相位鎖定速度快(2)過采樣型時(shí)鐘數(shù)據(jù)恢復(fù)電路中有大量數(shù)字單元,面積小、成本低且系統(tǒng)便于移植。這些優(yōu)勢(shì)使過采樣型時(shí)鐘數(shù)據(jù)恢復(fù)電路在高速低功耗應(yīng)用領(lǐng)域逐漸受到設(shè)計(jì)者的青睞。本文基于Xilinx 7系列FPGA平臺(tái),對(duì)過采樣型時(shí)鐘數(shù)據(jù)恢復(fù)電路的系統(tǒng)架構(gòu)和關(guān)鍵模塊單元進(jìn)行了深入的研究和分析,并針對(duì)1Gbps LVDS信號(hào)設(shè)計(jì)了一個(gè)高速串行數(shù)據(jù)采集及恢復(fù)系統(tǒng)。文章首先分析了各種時(shí)鐘數(shù)據(jù)恢復(fù)電路的基本結(jié)構(gòu),主要包括反饋相位跟蹤型、過采樣型和突發(fā)模式型。根據(jù)對(duì)電路結(jié)構(gòu)的分析和實(shí)際應(yīng)用平臺(tái),選取了過采樣型時(shí)鐘數(shù)據(jù)恢復(fù)電路結(jié)構(gòu)作為系統(tǒng)的基本架構(gòu)。根據(jù)傳統(tǒng)過采樣時(shí)鐘數(shù)據(jù)恢復(fù)電路的原理,提出了設(shè)計(jì)所需的算法,包括過采樣算法,邊沿檢測(cè)算法和數(shù)據(jù)恢復(fù)算法。完成算法設(shè)計(jì)后著重研究了如何使用Xilinx 7系列FPGA實(shí)現(xiàn)上述算法。本文設(shè)計(jì)的高速串行數(shù)據(jù)采集及恢復(fù)系統(tǒng)針對(duì)的是1Gbps高速串行數(shù)據(jù),由于硬件平臺(tái)的速率限制,傳統(tǒng)的過采樣結(jié)構(gòu)無法在FPGA平臺(tái)上實(shí)現(xiàn)。因此根據(jù)算法設(shè)計(jì),將采樣時(shí)鐘和輸入數(shù)據(jù)分別做復(fù)制和相移操作,利用兩路具有相位差的采樣時(shí)鐘對(duì)復(fù)制后的兩路數(shù)據(jù)進(jìn)行過采樣,并設(shè)計(jì)數(shù)據(jù)恢復(fù)模塊實(shí)時(shí)跟蹤系統(tǒng)的抖動(dòng)情況,選擇最優(yōu)采樣值。根據(jù)本文設(shè)計(jì),采樣時(shí)鐘頻率只需達(dá)到500MHz就可以實(shí)現(xiàn)對(duì)1Gbps輸入信號(hào)的4X過采樣,大大降低了過采樣電路對(duì)硬件平臺(tái)的運(yùn)行速度要求。最后,在ISE開發(fā)平臺(tái)中將HDL語言進(jìn)行綜合,得到系統(tǒng)的RTL級(jí)結(jié)構(gòu)。并使用多種類型的輸入信號(hào)對(duì)整個(gè)系統(tǒng)進(jìn)行仿真驗(yàn)證。在仿真結(jié)果正確后,通過映射、布局布線、管腳分配等工作生成位流文件,將設(shè)計(jì)下載至FPGA中。最后通過對(duì)實(shí)際信號(hào)的采集及恢復(fù)驗(yàn)證系統(tǒng)的功能。仿真及測(cè)試結(jié)果表明:在輸入信號(hào)速率達(dá)到1Gbps時(shí),系統(tǒng)能夠正常的實(shí)現(xiàn)數(shù)據(jù)采集及恢復(fù)功能,并且在多次采集及恢復(fù)的131072bit數(shù)據(jù)中均無誤碼產(chǎn)生。
[Abstract]:With the rapid development of high-speed serial communication system, it is very important to receive and recover data correctly and efficiently.The over-sampling clock data recovery circuit has the characteristics of simple structure and low power consumption. With the decrease of process size, the over-sampling clock data recovery circuit is compared with other clock data recovery circuit structures.For example, the widely used PLL structure gradually shows two major advantages: 1) the over-sampling clock data recovery circuit has no clock phase feedback circuit, and the phase locking speed is fast (2%) there are a large number of digital units in the over-sampling clock data recovery circuit.The area is small, the cost is low and the system is easy to transplant.These advantages make over-sampling clock data recovery circuit in high-speed and low-power applications gradually favored by designers.Based on Xilinx 7 series FPGA platform, the system architecture and key module units of over-sampling clock data recovery circuit are studied and analyzed in this paper. A high-speed serial data acquisition and recovery system is designed for 1Gbps LVDS signal.This paper first analyzes the basic structure of various clock data recovery circuits, including feedback phase tracking type, oversampling type and burst mode type.According to the analysis of the circuit structure and the practical application platform, the over-sampling clock data recovery circuit structure is selected as the basic structure of the system.According to the principle of the traditional over-sampling clock data recovery circuit, this paper presents the algorithms needed for the design, including over-sampling algorithm, edge detection algorithm and data recovery algorithm.After completing the algorithm design, this paper focuses on how to use Xilinx 7 series FPGA to realize the above algorithm.The high speed serial data acquisition and recovery system designed in this paper is aimed at 1Gbps high speed serial data. Because of the speed limitation of hardware platform, the traditional oversampling structure can not be realized on FPGA platform.Therefore, according to the algorithm design, the sampling clock and the input data are duplicated and phase-shifted respectively, and two sampling clocks with phase difference are used to oversample the two replicated data.The data recovery module is designed to track the jitter of the system, and the optimal sampling value is selected.According to the design of this paper, the 4X oversampling of 1Gbps input signal can be realized only when the sampling clock frequency is up to 500MHz, which greatly reduces the running speed of the oversampling circuit on the hardware platform.Finally, the RTL level structure of the system is obtained by synthesizing the HDL language in the ISE development platform.A variety of input signals are used to simulate the whole system.After the simulation results are correct, the design is downloaded to FPGA by mapping, routing and pin assignment.Finally, the function of the system is verified by collecting and recovering the actual signal.The simulation and test results show that when the input signal rate reaches 1Gbps, the system can normally realize the function of data acquisition and recovery, and there is no error code generation in the 131072bit data collected and recovered many times.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TP274.2;TN791

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本文編號(hào)：1767471