本文選題：集成電路制造 + 成品率��； 參考：《浙江大學(xué)》2015年碩士論文

【摘要】：隨著集成電路制造的工藝尺寸不斷減小,集成電路制造工藝越來(lái)越復(fù)雜,由缺陷引起的成品率問(wèn)題漸趨嚴(yán)重。晶體管的失配問(wèn)題也因?yàn)楣に嚦叽绲臏p小而變得嚴(yán)重,失配問(wèn)題對(duì)集成電路的性能的影響非常明顯,從而會(huì)造成成品率的問(wèn)題。SRAM單元中的晶體管由于尺寸更小,設(shè)計(jì)更加緊湊,設(shè)計(jì)規(guī)則更嚴(yán)格等問(wèn)題,SRAM單元中晶體管的失配問(wèn)題更加嚴(yán)峻。測(cè)試芯片作為監(jiān)測(cè)制造工藝缺陷,評(píng)估產(chǎn)品可靠性和提取器件工藝參數(shù)的工具,對(duì)提升集成電路制造工藝成品率起著舉足輕重的作用�？蓪ぶ窚y(cè)試芯片由于在放置測(cè)試結(jié)構(gòu)的數(shù)量上具有非常大的優(yōu)勢(shì)而成為測(cè)試芯片分支的研究熱點(diǎn)。本文圍繞更高面積利用率和測(cè)試精度的專用于SRAM失配特性研究的可尋址測(cè)試芯片展開(kāi)了研究： 1)針對(duì)SRAM的特殊結(jié)構(gòu),提出了一種專用于SRAM單元中晶體管對(duì)的失配特性研究的測(cè)試結(jié)構(gòu)的設(shè)計(jì)方法。對(duì)于SRAM單元中的PD、PG和PU三種類型的晶體管對(duì),分別設(shè)計(jì)了其對(duì)應(yīng)的測(cè)試結(jié)構(gòu)。這些測(cè)試結(jié)構(gòu)都是在原始的SRAM單元版圖的基礎(chǔ)上修改而得到的,修改的原則是保持其前端設(shè)計(jì)不變,修改部分金屬繞線隔離待測(cè)晶體管與其他晶體管的連接,并且修改后的測(cè)試結(jié)構(gòu)版圖保持對(duì)稱。 2)針對(duì)專用于SRAM單元晶體管對(duì)的失配特性的測(cè)試設(shè)計(jì)了放置在劃片槽的可尋址測(cè)試芯片。該方法實(shí)現(xiàn)了在68×2381um2的測(cè)試芯片面積內(nèi)放置120對(duì)DUT,并能夠準(zhǔn)確的測(cè)量每個(gè)DUT的晶體管性能參數(shù)：飽和狀態(tài)下的漏極和源極之間的電流、亞閾值電流、飽和狀態(tài)下的閾值電壓和線性狀態(tài)下的閾值電壓。這種測(cè)試芯片在28nm CMOS工藝下進(jìn)行了流片,并對(duì)其進(jìn)行了測(cè)試,驗(yàn)證了這種設(shè)計(jì)方法的可行性和測(cè)試精度。
[Abstract]:With the continuous reduction of the process size of IC manufacturing, the IC manufacturing process is becoming more and more complex, and the problem of yield caused by defects is becoming more and more serious.The problem of transistor mismatch also becomes serious because of the decrease of process size. The effect of mismatch problem on the performance of integrated circuit is very obvious, which will result in the yield problem. The transistor in SRAM cell is smaller in size and more compact in design.More strict design rules and other problems, SRAM cells in the transistor mismatch more serious.As a tool for monitoring manufacturing process defects, evaluating product reliability and extracting device process parameters, the test chip plays an important role in improving the production rate of integrated circuit manufacturing process.Addressable test chips have become the research focus of test chips due to their great advantages in the number of test structures.This paper focuses on the addressable test chip which is dedicated to the study of SRAM mismatch characteristics with higher area utilization ratio and test accuracy.1) aiming at the special structure of SRAM, a design method of test structure for the study of mismatch characteristics of transistor pairs in SRAM cells is presented.The corresponding test structures are designed for three types of transistors, PDPG and pu, in SRAM cells.These test structures were all modified on the basis of the original SRAM cell layout. The principle of the modification was to keep its front-end design unchanged, and to modify the connection of some metal wire wound isolated transistors to other transistors.And the revised layout of the test structure remains symmetrical.2) the addressable test chip is designed for the mismatch characteristic of SRAM unit transistor pair.In this method, 120 pairs of DUTs are placed in the area of 68 脳 2381um2 test chip, and the transistor performance parameters of each DUT can be accurately measured: the current between drain and source in saturated state, subthreshold current, etc.Threshold voltage in saturation state and threshold voltage in linear state.The test chip is carried out in 28nm CMOS process and tested. The feasibility and accuracy of the design method are verified.
【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN405

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 朱華平;戴慶元;徐健;;納米級(jí)CMOS電路的漏電流及其降低技術(shù)[J];微處理機(jī);2005年06期

，

本文編號(hào)：1763496