本文選題：封閉形柵 + 抗輻射設(shè)計(jì)加固��； 參考：《電子科技大學(xué)》2015年碩士論文

【摘要】：隨著半導(dǎo)體技術(shù)的飛速發(fā)展和器件工藝尺寸的減小,互補(bǔ)型金屬氧化物半導(dǎo)體(Complementary Metal Oxide Semiconductor,簡(jiǎn)寫為CMOS)集成電路的可靠性問題越來越明顯。尤其是在航天領(lǐng)域中,輻射所帶來的可靠性問題尤為突出,抗輻射加固產(chǎn)品的需求越來越高,對(duì)使用芯片及系統(tǒng)抗輻射能力的要求也越來越高。在眾多抗輻射加固方法中,采用封閉形柵晶體管的版圖設(shè)計(jì)對(duì)于總劑量輻射效應(yīng)是一種有效的抗輻射加固方法。于是,如何使用正確的寬長(zhǎng)比提取方法對(duì)封閉形柵進(jìn)行設(shè)計(jì),并估算其帶來的面積損耗以及封閉形柵NMOS晶體管的可靠性進(jìn)行研究成為了現(xiàn)階段半導(dǎo)體器件的研究熱點(diǎn)。基于以上背景,本文圍繞封閉形柵NMOS晶體管的設(shè)計(jì)與器件特性展開了研究。具體內(nèi)容如下:基于商用CMOS工藝線,我們?cè)O(shè)計(jì)并制備了不同柵氧化層厚度和不同柵形狀的封閉形柵NMOS晶體管,主要有環(huán)形柵、半環(huán)形柵和用于對(duì)比研究的條形柵。通過對(duì)完成制備的各種樣片進(jìn)行電特性測(cè)試,表明所設(shè)計(jì)的NMOS晶體管達(dá)到設(shè)計(jì)要求。并對(duì)條形柵、半環(huán)形柵和環(huán)形柵NMOS晶體管的最小寬長(zhǎng)比和所占的版圖面積進(jìn)行了對(duì)比研究,并對(duì)比研究了三種提取封閉形柵NMOS晶體管的有效寬長(zhǎng)比的方法,實(shí)驗(yàn)顯示環(huán)形柵常使用的中線近似法和半環(huán)形柵使用的均值法提取有效W/L都存在誤差,在可接受范圍內(nèi),是最簡(jiǎn)單有效的方法。通過對(duì)不同柵氧厚度的封閉形柵NMOS晶體管進(jìn)行輻射實(shí)驗(yàn)研究和計(jì)算機(jī)仿真研究,通過對(duì)工藝修正參數(shù)的調(diào)整,可以使實(shí)驗(yàn)數(shù)據(jù)和仿真數(shù)據(jù)達(dá)到很好的一致性,仿真結(jié)果和實(shí)驗(yàn)結(jié)果顯示在柵氧化層更薄的工藝線中,封閉形柵NMOS的抗總劑量輻射加固效果更加顯著,環(huán)形柵的加固效果優(yōu)于半環(huán)形柵。對(duì)比研究了基于0.18μm CMOS工藝的環(huán)形柵、半環(huán)形柵和條形柵NMOS晶體管的熱載流子效應(yīng),通過對(duì)其應(yīng)力前后電特性的對(duì)比研究分析,結(jié)果顯示,隨著直流應(yīng)力退化時(shí)間的累積,NMOS晶體管的漏電流會(huì)減小,閾值電壓變大、跨導(dǎo)的峰值也會(huì)變小。并且,同一寬長(zhǎng)比的NMOS,環(huán)形柵的退化最嚴(yán)重,半環(huán)形柵其次,與條形柵相差不大。所以,封閉形柵NMOS晶體管雖然能很好提高抗總劑量輻射能力,但對(duì)于抗HCI效應(yīng)沒有任何優(yōu)勢(shì)。
[Abstract]:With the rapid development of semiconductor technology and the decrease of device size, the reliability of complementary Metal Oxide Semiconductors is becoming more and more obvious.Especially in the field of spaceflight, the reliability problem caused by radiation is particularly prominent. The demand for radiation hardening products is more and more high, and the demand for radiation resistance ability of chips and systems is also higher and higher.The layout design of closed gate transistors is an effective method for the total dose radiation effect.Therefore, how to design the closed gate with the correct ratio of width to length and estimate the area loss and the reliability of the closed gate NMOS transistor has become the research focus of semiconductor devices at present.Based on the above background, the design and device characteristics of closed gate NMOS transistors are studied in this paper.The main contents are as follows: based on the commercial CMOS process line, we have designed and fabricated closed gate NMOS transistors with different gate oxide thickness and different gate shapes, including ring gate, semi-ring gate and strip gate for comparative study.The electrical properties of various samples are tested and the results show that the designed NMOS transistors meet the design requirements.The minimum aspect ratio and layout area of strip gate, half ring gate and ring gate NMOS transistor are compared, and three methods of extracting the effective aspect ratio of closed gate NMOS transistor are compared and studied.The experimental results show that there are errors in extracting effective W / L by the median approximation method and the mean value method used in the annular gate, which is the simplest and most effective method in the acceptable range.Through the radiation experiment and computer simulation of closed gate NMOS transistor with different gate oxygen thickness, the experimental data and the simulation data can be well consistent by adjusting the parameters of the process correction.The simulation and experimental results show that in the process line with thinner gate oxide the reinforcement effect of closed gate NMOS against total dose radiation is more remarkable and the reinforcement effect of annular gate is better than that of semi-annular gate.The hot carrier effect of ring gate, half ring gate and strip gate NMOS transistor based on 0. 18 渭 m CMOS process is studied.With the accumulation of DC stress degradation time, the leakage current of NMOS transistor decreases, the threshold voltage increases and the peak value of transconductance decreases.Moreover, for NMOS with the same aspect ratio, the degradation of annular gate is the most serious, and that of semi-annular gate is less than that of strip gate.Therefore, although the closed gate NMOS transistor can improve the total dose radiation resistance, it has no advantage in resisting the HCI effect.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN386

【相似文獻(xiàn)】

相關(guān)期刊論文 前10條

1 孫偉鋒,易揚(yáng)波,吳?,王平,吳建輝;一種新型凹源HV-NMOS器件研究[J];固體電子學(xué)研究與進(jìn)展;2004年03期

2 方偉,周晶,劉懋,楊東;仿真在NMOS電路設(shè)計(jì)中的應(yīng)用[J];微處理機(jī);2005年02期

3 胡志良;賀朝會(huì);;工藝參數(shù)對(duì)SOI NMOS總劑量效應(yīng)的影響[J];核技術(shù);2010年10期

4 邱恒功;李洛宇;裴國(guó)旭;杜明;;0.18μm SOI NMOS單粒子效應(yīng)中電荷累積機(jī)理的仿真研究[J];科學(xué)技術(shù)與工程;2013年21期

5 錢圣巳;靜態(tài)NMOS隨機(jī)取數(shù)存貯器[J];系統(tǒng)工程與電子技術(shù);1980年08期

6 張鐘宣,陳大同,唐政;一種NMOS四值靜態(tài)存貯單元的設(shè)計(jì)[J];固體電子學(xué)研究與進(jìn)展;1988年04期

7 鄭君里;龔明甫;李永明;;E/D NMOS CHOPPER-STABILIZED OP AMP[J];Journal of Electronics(China);1988年02期

8 趙小杰,吳訓(xùn)威;三值NMOS電路輸出級(jí)的改進(jìn)設(shè)計(jì)[J];固體電子學(xué)研究與進(jìn)展;1991年04期

9 劉以f，

本文編號(hào)：1743084