本文選題：電流舵 + 高速DAC　； 參考：《西安電子科技大學(xué)》2015年碩士論文

【摘要】：隨著無線通信的領(lǐng)域的迅猛發(fā)展,數(shù)模轉(zhuǎn)換器以及模數(shù)轉(zhuǎn)換器做為連接模擬信號(hào)與數(shù)字信號(hào)之間連接的樞紐,其重要性越來越高。由于數(shù)字電路處理速度的迅速提升,高性能的數(shù)模以及模數(shù)轉(zhuǎn)換器的發(fā)展就成為了制約整個(gè)通訊芯片產(chǎn)業(yè)發(fā)展的重要因素。同時(shí)隨著如今工藝尺寸的不斷縮小,模擬芯片的設(shè)計(jì)難度也在不斷的提高,這就給高性能DAC的設(shè)計(jì)者帶來了巨大的挑戰(zhàn)。電流舵DAC由于其能夠支持極高采樣率以及對(duì)于標(biāo)準(zhǔn)工藝的優(yōu)秀兼容性,一直以來都是超高速DAC設(shè)計(jì)者們常用的主要結(jié)構(gòu)。但是電流舵DAC也不可避免的存在著許多不足的地方,開關(guān)信號(hào)產(chǎn)生的毛刺能量以及電流源陣列內(nèi)所存在的各種靜態(tài)以及動(dòng)態(tài)失配會(huì)很大程度上限制DAC的線性度。本文針對(duì)以上影響進(jìn)行了優(yōu)化與改進(jìn)從而提升了DAC的線性度。本文基于SMIC0.18μm的標(biāo)準(zhǔn)CMOS生產(chǎn)工藝進(jìn)行設(shè)計(jì),設(shè)計(jì)了一款采樣速率最高能夠達(dá)到3GSPS的14位高速高精度電流舵DAC。此DAC采用了高4位低10位的分段式譯碼結(jié)構(gòu)對(duì)輸入信號(hào)進(jìn)行譯碼,其中高位采用了改進(jìn)型的分組隨機(jī)旋轉(zhuǎn)二進(jìn)制譯碼結(jié)構(gòu)對(duì)輸入的數(shù)字信號(hào)進(jìn)行譯碼。采用此譯碼方式能夠有效的在電路的復(fù)雜度以及電路動(dòng)態(tài)匹配性能之間尋找平衡點(diǎn),隨后使用四通道數(shù)據(jù)內(nèi)插技術(shù)對(duì)經(jīng)過譯碼之后的四路低頻采樣信號(hào)進(jìn)行內(nèi)插組合而成一個(gè)最高能夠達(dá)到3GSPS的高頻采樣信號(hào)從而達(dá)到提升DAC動(dòng)態(tài)性能的目的,本文所采用的單位電流源使用的共源共柵的結(jié)構(gòu)來提升電流源的的輸出阻抗,同時(shí)采用了四相開關(guān)結(jié)構(gòu)來降低控制信號(hào)翻轉(zhuǎn)產(chǎn)生的毛刺對(duì)于DAC線性度的影響,提高DAC的整體性能。對(duì)整體電路進(jìn)行了基本功能的仿真以及無雜散動(dòng)態(tài)范圍(SFDR)的仿真,仿真結(jié)果顯示在采樣頻率達(dá)到3GHz的情況下SFDR達(dá)到了75dB。在版圖的繪制階段使用了Cadence環(huán)境下的Virtuoso圖形化版圖設(shè)計(jì)工具對(duì)版圖進(jìn)行了設(shè)計(jì),嚴(yán)格按照SMIC工藝的要求以及模擬版圖設(shè)計(jì)方法進(jìn)行仔細(xì)的設(shè)計(jì),而且在設(shè)計(jì)的過程中考慮到工藝失配的影響運(yùn)用了電流源陣列匹配技術(shù)對(duì)電流源陣列的版圖進(jìn)行優(yōu)化設(shè)計(jì)。
[Abstract]:With the rapid development of wireless communication, digital to analog converters and analog-to-digital converters are becoming more and more important for connecting analog and digital signals.With the rapid improvement of the processing speed of digital circuits, the development of high performance digital-to-analog (A / A) and analog-to-digital converters (ADC) has become an important factor restricting the development of the whole communication chip industry.At the same time, with the continuous reduction of process size, the design difficulty of analog chip is also increasing, which brings great challenges to the designers of high-performance DAC.Because of its ability to support extremely high sampling rate and excellent compatibility with standard process, the current steering DAC has always been the main structure commonly used by DAC designers.However, there are many disadvantages in the current steering DAC. The burr energy generated by the switch signal and the various static and dynamic mismatch in the current source array will limit the linearity of the DAC to a great extent.In order to improve the linearity of DAC, the above effects are optimized and improved in this paper.Based on the standard CMOS process of SMIC0.18 渭 m, a 14 bit high speed and high precision current rudder DAC with the highest sampling rate up to 3GSPS is designed in this paper.In this DAC, the input signal is decoded with a segmented decoding structure with high 4 bits and low 10 bits, and the input digital signal is decoded in high position with an improved packet random rotation binary decoding structure.This decoding method can effectively find the balance point between the complexity of the circuit and the dynamic matching performance of the circuit.Then the four-channel data interpolation technique is used to interpolate the four channels of low-frequency sampling signals after decoding to form a high-frequency sampling signal which can achieve the maximum 3GSPS, thus achieving the purpose of improving the dynamic performance of DAC.In this paper, the output impedance of the current source is raised by using the common gate structure of the unit current source and the four-phase switching structure is used to reduce the effect of burrs produced by the control signal flipping on the linearity of the DAC.Improve the overall performance of DAC.The basic functions of the whole circuit and the simulation of SFDR without spurious dynamic range are simulated. The simulation results show that the SFDR reaches 75 dB when the sampling frequency reaches 3GHz.In the drawing stage of layout, the Virtuoso graphic layout design tool under Cadence environment is used to design the layout. The layout is carefully designed according to the requirements of SMIC process and the method of analog layout design.Considering the influence of process mismatch, the current source array matching technique is used to optimize the layout of current source array.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN792

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