本文選題：抗輻射 + VDMOS��； 參考：《東南大學》2015年碩士論文

【摘要】：應(yīng)用于航天器領(lǐng)域的VDMOS器件受到輻射會產(chǎn)生總劑量輻射電離效應(yīng)(TID),從而使得器件出現(xiàn)閡值電壓漂移、導(dǎo)通電阻變化和擊穿電壓下降等現(xiàn)象,這些現(xiàn)象會極大地影響VDMOS器件的性能、進而導(dǎo)致航天器壽命下降。同時,輻射也會產(chǎn)生單粒子效應(yīng)(SEB、SEGR)使得VDMOS器件燒毀失效。因此,對VDMOS器件輻射加固方法的研究意義重大。本文在普通VDMOS器件的基本結(jié)構(gòu)、主要參數(shù)等基礎(chǔ)上重點研究了輻射產(chǎn)生的三種效應(yīng),即SEB、SEGR和TID。借助TSUPREM4、MEDICI,研究了VDMOS器件發(fā)生SEB、SEGR失效的過程,揭示了VDMOS器件產(chǎn)生SEB、SEGR的物理機理。通過分析器件漏源擊穿特性曲線,得出了VDMOS器件二次擊穿點電壓與SEB安全工作區(qū)域的關(guān)系。通過分析器件電場縱向分布和凈剩電荷縱向分布,提出了用電荷曲線積分原理解釋VDMOS器件電場縱向分布的方法。借助SEGR半經(jīng)驗公式,建立了SEGR分析模型,并用該模型研究了離子種類、入射位置、JFET區(qū)寬度對VDMOS器件發(fā)生SEGR的臨界條件的影響,分別得出輻射離子原子序數(shù)越大越容易發(fā)生SEGR、入射位置越靠近JFET區(qū)中間越易發(fā)生SEGR、 JFET區(qū)寬度越窄越有利于器件抵抗SEGR的結(jié)論。然后,重點分析了VDMOS器件抗SEB、SEGR的輻射加固方法,研究了P+/N+工藝參數(shù)對VDMOS器件SEB安全電壓的影響,得出P+與N+濃度相差越大SEB安全電壓越小的結(jié)論。通過比較帶緩沖層和不帶緩沖層兩種結(jié)構(gòu)SEB安全電壓的大小,證實了帶有緩沖層的結(jié)構(gòu)有利于抗SEB的結(jié)論,并利用MEDICI仿真給出了緩沖層的最佳參數(shù)。最后,提出了一種新型抗SEGR的VDMOS器件結(jié)構(gòu),比較了新型結(jié)構(gòu)和傳統(tǒng)結(jié)構(gòu)的SEGR臨界條件,證實了該結(jié)構(gòu)抗SEGR性能良好的結(jié)論。本文完成了課題的設(shè)計目標：250V/12A、導(dǎo)通電阻0.22Ω、閾值電壓2-4V的抗輻射VDMOS器件。借助TSUPREM4和MEDICI軟件軟件設(shè)計了器件的電學參數(shù)、確定了最終的工藝流程,并利用Cadence軟件繪制了不同方案的器件版圖。仿真結(jié)果表明器件設(shè)計滿足指標要求。
[Abstract]:The ionizing effect of total dose radiation on the VDMOS devices used in spacecraft field will be caused by the total dose radiation ionization effect, which will lead to the threshold voltage drift, the change of on-resistance and the decrease of breakdown voltage, etc.These phenomena will greatly affect the performance of VDMOS devices and lead to the decline of spacecraft life.At the same time, the single particle effect is also produced by the radiation, which causes the VDMOS device to burn out.Therefore, it is of great significance to study the radiation reinforcement method of VDMOS devices.In this paper, based on the basic structure and main parameters of VDMOS devices, three kinds of radiation effects, namely SEBX SEGR and TID, are studied.By means of TSUPREM4 MEDICI, the failure process of VDMOS devices is studied, and the physical mechanism of SEBU SEGR generation by VDMOS devices is revealed.The relationship between the secondary breakdown point voltage of VDMOS device and the safe working area of SEB is obtained by analyzing the breakdown characteristic curve of the device drain source.Based on the analysis of the longitudinal distribution of electric field and net residual charge of VDMOS devices, a method to interpret the longitudinal distribution of electric field in VDMOS devices by means of charge curve integral principle is proposed.Based on the SEGR semi-empirical formula, the SEGR analysis model is established, and the influence of ion species, incident position and JFET width on the critical conditions for SEGR occurrence in VDMOS devices is studied.It is concluded that the larger the atomic number of the radiation ions, the easier the SEGRs are, the closer the incident position is to the middle of the JFET region, the easier the SEGRs are, and the narrower the width of the JFET region is, the more favorable the device is to resist the SEGR.Then, the radiation reinforcement method of VDMOS device is analyzed, and the influence of P / N process parameters on the safe voltage of VDMOS device SEB is studied. The conclusion is drawn that the greater the difference between P and N concentration is, the smaller the S EB safe voltage is.By comparing the security voltage of SEB with and without buffer layer, the conclusion that the structure with buffer layer is favorable to resist SEB is confirmed, and the optimum parameters of buffer layer are given by MEDICI simulation.Finally, a new type of VDMOS device structure is proposed to resist SEGR. The SEGR critical conditions of new structure and traditional structure are compared, and the conclusion that the structure has good anti-#en3# performance is proved.In this paper, the objective of the design is: 250V / 12A, on-resistance 0.22 惟, threshold voltage 2-4V anti-radiation VDMOS device.The electrical parameters of the device are designed with the help of TSUPREM4 and MEDICI software, the final process is determined, and the device layout of different schemes is plotted by using Cadence software.The simulation results show that the device design meets the requirements.
【學位授予單位】：東南大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN386

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