本文選題：頻率合成器　切入點：鎖相環(huán)　出處：《電子科技大學(xué)》2015年碩士論文

【摘要】：隨著半導(dǎo)體技術(shù)的發(fā)展,頻率合成技術(shù)也有了很大的進(jìn)步,從最初的直接頻率合成技術(shù)到間接頻率合成技術(shù)再到最新的直接數(shù)字頻率合成技術(shù)。技術(shù)的進(jìn)步同樣使得電子系統(tǒng)對頻率合成器的指標(biāo)有了越來越高的要求。作為電子系統(tǒng)的心臟,頻率合成器性能的好壞會直接影響到整個系統(tǒng)的性能。本文提出了一種2.5GHz-14.6GHz超寬帶低相位噪聲頻率合成器的實現(xiàn)方法。本文首先介紹了頻率合成技術(shù)的發(fā)展歷程,并介紹了每個發(fā)展階段中重要的頻率合成技術(shù)的特點以及頻率合成器的關(guān)鍵指標(biāo),然后介紹了2.5GHz-14.6GHz超寬帶頻率合成器的需求指標(biāo),通過指標(biāo)分析了實現(xiàn)此頻率合成器需要用到的關(guān)鍵技術(shù)以及方法。通過分析,最終選定使用PLL+DDS的結(jié)構(gòu)實現(xiàn)頻率合成器,通過對鎖相環(huán)系統(tǒng)的分析,將鎖相環(huán)系統(tǒng)分解成鑒相器、預(yù)分頻器、小數(shù)分頻器、振蕩器等幾個部分,其中頻率步進(jìn)主要由小數(shù)分頻器決定;雜散主要由鑒相器和小數(shù)分頻器決定;各部分對相位噪聲都有一定影響。通過對每部分的分析,對每一部分都給出了一兩種可選方案。本文隨后對分析中所提到的每部分的方案進(jìn)行了設(shè)計與實現(xiàn),在設(shè)計過程中對備選方案進(jìn)行了最終的確認(rèn),同時對一些分析過程中沒有注意到的以及不合理的地方進(jìn)行了補(bǔ)充以及更正。同時給出了每個模塊設(shè)計過程中需要注意的問題并給出了相應(yīng)的解決方案。然后給出了每部分的原理圖、PCB板圖以及實物圖。最后給出了屏蔽腔體的設(shè)計圖。通過測試,文章設(shè)計的頻率源頻率步進(jìn)小于1Hz,非諧波雜散抑制基本滿足-75dBc的要求,輸出功率滿足10dBm的要求,全頻段相位噪聲優(yōu)于-85dBc/Hz@10kHz。基本滿足了設(shè)計指標(biāo)的需求。文章最后對頻率源存在的問題以及改進(jìn)方法進(jìn)行了簡單闡述。
[Abstract]:With the development of semiconductor technology, frequency synthesis technology has made great progress, from the initial direct frequency synthesis technology to indirect frequency synthesis technology to the latest direct digital frequency synthesis technology.The progress of technology also makes the electronic system to the frequency synthesizer index has the higher and higher request.As the heart of electronic system, the performance of frequency synthesizer will directly affect the performance of the whole system.In this paper, a realization method of 2.5GHz-14.6GHz ultra-wideband low phase noise frequency synthesizer is presented.In this paper, the development of frequency synthesis technology is introduced, and the characteristics of frequency synthesizer and the key index of frequency synthesizer are introduced. Then the requirement index of 2.5GHz-14.6GHz UWB frequency synthesizer is introduced.The key techniques and methods used to realize the frequency synthesizer are analyzed.Through analysis, the structure of PLL DDS is selected to realize the frequency synthesizer. By analyzing the PLL system, the PLL system is decomposed into several parts, such as phase discriminator, predivider, fractional frequency divider, oscillator and so on.The frequency step is mainly determined by the fractional frequency divider, the spurious is mainly determined by the phase discriminator and the fractional frequency divider, and each part has certain influence on the phase noise.Through the analysis of each part, we give one or two alternative schemes for each part.Then, this paper designs and implements each part of the program mentioned in the analysis, and finally confirms the alternatives in the design process.At the same time, some unnoticed and unreasonable areas are supplemented and corrected.At the same time, the problems that should be paid attention to in the design of each module are given and the corresponding solutions are given.Then, the schematic diagram of each part and the physical diagram are given.Finally, the design diagram of the shielded cavity is given.The results show that the frequency step of the designed frequency source is less than 1Hz, the non-harmonic spurious suppression meets the requirement of -75dBc, the output power meets the requirement of 10dBm, and the phase noise in the whole frequency band is better than -85dBc / Hzr / Hz10kHz.Basically meet the requirements of the design indicators.At the end of the paper, the problems of frequency source and the improvement methods are briefly described.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN74

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 孟玉潔,賈懷義,陶成;DDS中幾種關(guān)鍵的ROM壓縮方法[J];天津通信技術(shù);2004年01期

，

本文編號：1723935