本文選題：FPGA　切入點：DSP　出處：《現(xiàn)代電子技術(shù)》2013年14期

【摘要】：簡要介紹了FIR數(shù)字濾波器的結(jié)構(gòu)特點和基本原理,提出基于FPGA和DSP Builder的FIR數(shù)字濾波器的基本設(shè)計流程和實現(xiàn)方案。在Matlab/Simulink環(huán)境下,采用DSP Builder模塊搭建FIR模型,根據(jù)FDATool工具對FIR濾波器進(jìn)行了設(shè)計,然后進(jìn)行系統(tǒng)級仿真和ModelSim功能仿真,其仿真結(jié)果表明其數(shù)字濾波器的濾波效果良好。通過SignalCompiler把模型轉(zhuǎn)換成VHDL語言加入到FPGA的硬件設(shè)計中,從QuartusⅡ軟件中的虛擬邏輯分析工具SignalTapⅡ中得到數(shù)字濾波器實時的結(jié)果波形圖,結(jié)果符合預(yù)期。
[Abstract]:This paper briefly introduces the structure and principle of FIR digital filter, and puts forward the basic design flow and implementation scheme of FIR digital filter based on FPGA and DSP Builder.In the Matlab/Simulink environment, the FIR model is built with DSP Builder module, and the FIR filter is designed according to the FDATool tool. Then the system level simulation and ModelSim function simulation are carried out. The simulation results show that the digital filter has good filtering effect.The model is transformed into VHDL language by SignalCompiler and added to the hardware design of FPGA. The result waveform of digital filter in real time is obtained from SignalTap 鈪，

本文編號：1719548