本文選題：混合信號驗證　切入點：wreal模型　出處：《電子技術(shù)應(yīng)用》2017年08期

【摘要】：混合信號驗證在當(dāng)前So C設(shè)計中的作用越來越重要,被稱為芯片流片以前的健康體檢,可以有效避免芯片二次流片。結(jié)果證實大部分芯片的問題可以通過合適的混合信號驗證方法發(fā)現(xiàn)。當(dāng)前混合信號驗證的主要挑戰(zhàn)包括行為級模型建模、晶體管級仿真速度、低功耗驗證等,介紹了微控制器芯片KW41中使用的一整套混合信號驗證方法,包括使用電路模型產(chǎn)生器生成wreal模型,混合模式數(shù)�；旌闲盘柗抡�,模擬電路斷言和電路檢測幫助實現(xiàn)自動化檢驗,模擬電路檢測發(fā)現(xiàn)模擬電路潛在問題,用XPS MS做全芯片晶體管級仿真。該方法適用于所有數(shù)字設(shè)計為主的芯片。
[Abstract]:Mixed signal verification plays a more and more important role in the current so C design. It is called the physical examination before the chip flow sheet, which can effectively avoid the secondary flow chip.The results show that most of the chip problems can be detected by a suitable mixed signal verification method.At present, the main challenges of mixed signal verification include behavioral model modeling, transistor-level simulation speed, low-power verification and so on. This paper introduces a set of mixed signal verification methods used in microcontroller chip KW41.Including the use of circuit model generator to generate wreal model, mixed mode digital-analog mixed signal simulation, analog circuit assertion and circuit detection to help achieve automatic testing, analog circuit detection found potential problems in analog circuits,XPS MS is used to simulate the whole chip transistor level.This method is suitable for all digital design chips.
【作者單位】： 哈爾濱工業(yè)大學(xué)航天學(xué)院;恩智浦半導(dǎo)體蘇州研發(fā)中心;
【分類號】：TN40

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1 徐玉婷;基于子圖同構(gòu)的晶體管級電路門級模型抽取的研究[D];電子科技大學(xué);2007年

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本文編號：1702798