本文選題：FPGA　切入點(diǎn)：高速數(shù)字電路　出處：《中北大學(xué)》2015年碩士論文

【摘要】：隨著無線通信與計算技術(shù)以及信號處理與分析技術(shù)的發(fā)展，數(shù)字頻率合成技術(shù)已在雷達(dá)、通信、地震勘探、智能儀器、科學(xué)實(shí)驗(yàn)等各個方面有了廣泛的應(yīng)用。針對傳統(tǒng)數(shù)字合成系統(tǒng)存在的便捷性差、人機(jī)交互不友好、實(shí)時性差、智能化程度低等弱點(diǎn)，本文設(shè)計了以FPGA為核心的數(shù)字信號處理硬件電路，采用VHDL硬件描述語言實(shí)現(xiàn)FPGA內(nèi)邏輯設(shè)計，在VC2010平臺上用C++語言開發(fā)了上位機(jī)軟件，以上三部分的設(shè)計組成了數(shù)字頻率合成的信號源系統(tǒng)。 系統(tǒng)擬采用高速FPGA作為數(shù)字信號處理的核心元件，主要實(shí)現(xiàn)對系統(tǒng)的時序控制，任務(wù)調(diào)度，邏輯粘合、波形文件存儲控制、讀取，數(shù)據(jù)的并串轉(zhuǎn)換、輸出以及與上位機(jī)的通信控制。根據(jù)FPGA所需要處理的信號設(shè)計了高速DA數(shù)模轉(zhuǎn)換硬件電路。應(yīng)用VC2010作為軟件平臺設(shè)計了操控界面，其主要用于實(shí)現(xiàn)函數(shù)波形的計算、生成及加載。采用硬件描述語言對所需電路模塊進(jìn)行了嵌入式硬件設(shè)計。測試結(jié)果表明該信號源有良好的交互性，頻率準(zhǔn)確性和寬范圍應(yīng)用性。 在FPGA模塊設(shè)計中，用VHDL語言編制了相應(yīng)的時序電路和緩沖FIFO，并充分利用FPGA中豐富的時序資源，如鎖相環(huán)PLL、觸發(fā)器，緩沖器FIFO等，完成對系統(tǒng)輸入輸出時鐘的控制。本設(shè)計對數(shù)字邏輯設(shè)計中的部分模塊給出了相應(yīng)的仿真結(jié)果和詳細(xì)的說明以及時序分析。同時，，根據(jù)芯片AD9736數(shù)模轉(zhuǎn)換器件的時序配置要求，在Xilinx ISEdesign12.3環(huán)境下設(shè)計了輸出控制的狀態(tài)機(jī)。
[Abstract]:With the development of wireless communication and computing technology as well as signal processing and analysis technology, digital frequency synthesis technology has been widely used in radar, communication, seismic exploration, intelligent instruments, scientific experiments and so on.Aiming at the disadvantages of the traditional digital synthesis system, such as poor convenience, unfriendly human-computer interaction, poor real-time and low intelligence, the hardware circuit of digital signal processing based on FPGA is designed in this paper.The hardware description language of VHDL is used to realize the logic design of FPGA, and the software of upper computer is developed in C language on the platform of VC2010. The signal source system of digital frequency synthesis is made up of the design of the above three parts.The system adopts high speed FPGA as the core component of digital signal processing, which mainly realizes the timing control, task scheduling, logic bonding, waveform file storage control, reading, data parallel string conversion, etc.Output and communication control with host computer.A high speed DA digital-analog conversion hardware circuit is designed according to the signal needed by FPGA.The control interface is designed by using VC2010 as the software platform, which is mainly used to calculate, generate and load the function waveform.The embedded hardware is designed with hardware description language.The test results show that the signal source has good interactivity, frequency accuracy and wide application.In the design of FPGA module, the corresponding sequential circuit and buffer FIFO are programmed in VHDL language, and the abundant timing resources in FPGA, such as PLL, trigger, FIFO, etc., are fully utilized to control the system input and output clock.The simulation results, detailed explanation and timing analysis of some modules in digital logic design are given in this design.At the same time, the output control state machine is designed under the Xilinx / ISEdesign12.3 environment according to the timing configuration requirements of the chip AD9736 digital-to-analog converter.
【學(xué)位授予單位】：中北大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN74

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