本文選題：波形數(shù)字化　切入點：并行交替采樣　出處：《中國科學技術(shù)大學》2017年博士論文

【摘要】：在傳統(tǒng)物理試驗中,發(fā)展出了一系列的方法來測量探測器輸出信號的電荷和時間信息,然而這些參數(shù)只能表征有限的信號特征。若可以獲取信號的原始波形,則通過波形分析可以得到信號中包含的所有物理信息。因此波形數(shù)字化是物理學家一直以來夢寐以求的目標,也是物理實驗電子學領(lǐng)域的一個研究熱點。隨著高速模擬-數(shù)字變換(Analog-to-Digital Conversion,ADC)技術(shù)的發(fā)展,ADC的采樣率越來越高,但是在一些特殊的應用中,仍不能滿足我們對波形數(shù)字化采樣率的要求。如此一來,并行交替采樣(Time-Interleaved A/D Conversion,TIADC)技術(shù)的出現(xiàn)和發(fā)展,不僅在提高單個ADC芯片采樣率的設計中得以發(fā)揮巨大的促進作用,同時也使得我們可以利用采樣率有限的ADC芯片實現(xiàn)更高等效采樣速度的波形數(shù)字化系統(tǒng)。然而,并行交替采樣技術(shù)中多個并行采樣通道間的失配(增益、時鐘相位和直流偏置)是制約TIADC性能提升的主要瓶頸,因此必須解決失配誤差帶來的性能影響,才能保證TIADC系統(tǒng)本身的實用性。因此TIADC失配誤差的修正技術(shù)就是一個重要的研究方向。在傳統(tǒng)的完美重構(gòu)修正技術(shù)中,可以實現(xiàn)窄帶輸入信號情況下失配誤差的有效修正,然而在實際物理實驗中探測器輸出信號往往是寬帶信號,因此有必要發(fā)展一種適合寬帶信號下的修正方法,這就是本論文主要的研究方向,同時本論文還著重研究了上述算法的實時硬件實現(xiàn),并集成在單個FPGA(Field-Programmable Gate Array)芯片中。本論文的第一章介紹了波形數(shù)字化技術(shù)的基本概念,并簡要回顧了其中兩個具體的實現(xiàn)技術(shù),包括開關(guān)電容陣列和高速ADC,并特別介紹了高速、高精度ADC集成電路技術(shù)當前的最新發(fā)展水平和技術(shù)方向。第二章介紹了 ADC的基本原理和特征參數(shù),并對并行交替采樣技術(shù)的原理和遇到的技術(shù)挑戰(zhàn)進行了介紹,同時還回顧了了現(xiàn)有的兩大類TIADC系統(tǒng)中通道間失配誤差修正方法,一類是基于硬件自適應反饋調(diào)節(jié)或者軟件自適應修正的后臺修正技術(shù),另一類是基于前景校準的數(shù)字修正技術(shù)。第三章中進行了寬帶輸入信號情況下通道間失配誤差修正方法的理論推導,并介紹了其并行化的實現(xiàn)結(jié)構(gòu),還對修正方法的可行性基于MATLAB平臺進行了仿真。進一步地基于此修正方法的特點,對當前常用的FPGA內(nèi)部DSP(Digital Signal Processing)結(jié)構(gòu)進行了簡要的分析,為硬件具體的設計與實現(xiàn)提供了參考。第四章介紹了一 12位8 Gsps TIADC系統(tǒng)的硬件的設計方案。此TIADC系統(tǒng)主要用于上述修正算法正確性和所能達到性能的驗證測試。設計中使用2片12位4 Gsps(sample per second,每秒采樣次數(shù))的ADC芯片,基于并行交替采樣技術(shù)實現(xiàn)等效8 Gsps的采樣速度,并將所有的修正算法集成在一片F(xiàn)PGA芯片中。第五章介紹了此TIADC硬件系統(tǒng)的具體實現(xiàn),并詳細介紹了 FPGA邏輯的具體設計方案,其中重點介紹了并行修正算法的具體結(jié)構(gòu)。第六章給出了硬件系統(tǒng)的測試結(jié)果。測試表明,在1.5GHz寬帶范圍內(nèi),修正后TIADC系統(tǒng)在550 MHz以下有效位好于8.7 Bits,在550 MHz～1500 MHz之間有效位好于8 Bits,基本達到ADC單芯片的性能水平,與其手冊中性能指標參數(shù)基本相當。此結(jié)果表明此修正算法可以明顯抑制通道間失配誤差的影響。最后一章對論文工作進行總結(jié),并展望下一步工作。
[Abstract]:In the traditional physics experiment, developed a series of methods to measure the charge and time information of the output signal of the detector, but these parameters can only characterize the limited signal characteristics. If the original waveform signal can be obtained, through the waveform analysis can get all the physical information of the signal waveform. Therefore digital physicists have always dreamed of the target, it is also a research focus of physics experiment electronics field. With the high-speed analog to digital converter (Analog-to-Digital Conversion ADC) technology, the sampling rate of ADC is more and more high, but in some special application, we still can not meet the requirements of digital waveform sampling rate. Thus, the parallel alternating sampling (Time-Interleaved A/D Conversion, TIADC) technology emergence and development, not only in a single ADC chip design to improve the sampling rate of Play a huge role in promoting, but also allows us to use sampling digital waveform system ADC chip rate limited to achieve higher equivalent sampling speed. However, the parallel alternating sampling technology of multiple parallel sampling channel mismatches (gain, clock phase and DC bias) is a major bottleneck in improving the performance of TIADC. It must address the effects of mismatch errors caused by the performance, in order to ensure the practicality of the TIADC system itself. Therefore TIADC mismatch error correction technology is an important research direction. In the perfect reconstruction of the traditional correction technique, can achieve narrowband input signal circumstances effectively mismatch correction, however, in the actual physical detector the output signal is the broadband signal, so it is necessary to develop a suitable correction method of the wideband signal, which is the main research direction, at the same time Real-time hardware implementation of this paper also focuses on the above algorithm, and integrated in a single FPGA (Field-Programmable Gate Array) chip. In the first chapter of this thesis introduces the basic concepts of digital waveform technology, and briefly reviews the two specific implementation techniques, including switching capacitor array and high speed ADC, and especially introduces the high speed, high precision ADC integrated circuit technology the latest development level and technical direction. The second chapter introduces the basic principle and characteristic parameters of ADC, and the principle of parallel alternating sampling technology and some technical challenges are introduced, and also reviews the channel two kinds of existing TIADC system in lost with error correction method, a kind of hardware or software adaptive feedback correction technique based on adaptive background correction, the other is the prospect of calibration of digital correction technique based on the third chapter. In the case of broadband signal input channel mismatch theory error correction method, and introduces its parallel implementation structure, but also the feasibility of correction method based on the MATLAB platform simulation. Further on this foundation characteristics of correction method, the current commonly used FPGA DSP (Digital Signal Processing) the structure was briefly analyzed, providing reference for the design and implementation of the hardware. The fourth chapter introduces the design of a 12 bit 8 Gsps TIADC system hardware. This TIADC system is mainly used in the algorithm is correct and can achieve the performance verification test. Using 2 pieces of 12 Gsps design (4 sample per second, the number of samples per second) of the ADC chip, the parallel sampling speed alternating sampling technique to achieve equivalent 8 based on Gsps, and the modified algorithm all integrated in a FPGA chip. The fifth chapter introduces The implementation of the TIADC hardware system, and introduces the concrete design of FPGA logic, which focuses on the specific structure of parallel correction algorithm. The sixth chapter gives the hardware test results. The test shows that the bandwidth of 1.5GHz, the modified TIADC system under 550 MHz effective bit better than 8.7 Bits, from 550 MHz to 1500 MHz between the effective bit better than 8 Bits, the level of performance reached the ADC single chip, and manual performance parameters. The results show that the equivalent correction algorithm can significantly inhibit the effect of channel mismatch error. The last chapter is the summary of the work, and looking forward to the next further work.

【學位授予單位】：中國科學技術(shù)大學
【學位級別】：博士
【學位授予年份】：2017
【分類號】：TN792

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本文編號：1693576