本文選題：局部可重構(gòu)　切入點(diǎn)：ASIP　出處：《西安電子科技大學(xué)》2015年碩士論文

【摘要】：隨著科學(xué)技術(shù)的不斷發(fā)展,以數(shù)據(jù)密集型應(yīng)用為代表的數(shù)據(jù)處理需求越來越復(fù)雜,而傳統(tǒng)的系統(tǒng)設(shè)計(jì)方法多采用通用處理器或?qū)Ｓ眉呻娐?ASIC),通用處理器具有性能上的局限性,ASIC雖然能夠提供較高的性能,但是其結(jié)構(gòu)決定了它制造完成之后無法進(jìn)行修改,靈活性不足,設(shè)計(jì)成本偏高。具有可重構(gòu)功能單元的ASIP,具有良好的靈活性和較高得性能,能夠?qū)崿F(xiàn)FPGA內(nèi)部邏輯資源的分時(shí)復(fù)用,使內(nèi)部資源得到最大限度的使用。動(dòng)態(tài)局部重構(gòu)技術(shù),能夠在系統(tǒng)正常工作的情況下,實(shí)現(xiàn)重構(gòu)區(qū)域內(nèi)邏輯的重新配置,在線修改動(dòng)態(tài)模塊的功能,具有節(jié)約硬件資源和增強(qiáng)系統(tǒng)靈活性的優(yōu)勢。本文選擇Xilinx Virtex-6 XC6VSX315T芯片,在搭建的系統(tǒng)平臺(tái)上實(shí)現(xiàn)了具有重構(gòu)功能單元的ASIP設(shè)計(jì),實(shí)現(xiàn)了對(duì)反正切運(yùn)算和求模運(yùn)算的局部重構(gòu)工作。本文主要完成的研究工作包括:(1)討論了該課題的研究背景和意義,建立了一個(gè)可靠的局部重構(gòu)設(shè)計(jì)流程,包括對(duì)電路功能的Verilog HDL描述,靜態(tài)區(qū)域與動(dòng)態(tài)區(qū)域的設(shè)計(jì),配置實(shí)現(xiàn)與配置文件驗(yàn)證等步驟;(2)結(jié)合CORDIC理論方法,使用流水線設(shè)計(jì)方式,設(shè)計(jì)了反正切運(yùn)算的具體電路,能夠通過移位和加減法運(yùn)算實(shí)現(xiàn)反正切運(yùn)算,且誤差在系統(tǒng)允許范圍內(nèi);(3)實(shí)現(xiàn)了具有重構(gòu)功能單元的ASIP的設(shè)計(jì),能夠根據(jù)指令集要求,實(shí)現(xiàn)基本運(yùn)算,并且能夠?qū)崿F(xiàn)反正切運(yùn)算和平方根運(yùn)算的重構(gòu)。對(duì)系統(tǒng)進(jìn)行了仿真實(shí)驗(yàn),實(shí)驗(yàn)證明,系統(tǒng)能夠?qū)崿F(xiàn)硬件資源的分時(shí)復(fù)用,提高了邏輯資源的利用率。
[Abstract]:With the development of science and technology, the demand of data processing, represented by data-intensive applications, is becoming more and more complex. However, the traditional system design methods usually use general purpose processor or ASIC. Although the general purpose processor has the limitation of performance, although it can provide higher performance, its structure determines that it can not be modified after the completion of manufacture. Because of the lack of flexibility and high design cost, the FPGA with reconfigurable function unit has good flexibility and high performance, and can realize the time-sharing reuse of the internal logic resources of FPGA. The dynamic local reconfiguration technology can reconfigure the logic in the reconfigurable region and modify the function of the dynamic module online when the system works normally. It has the advantages of saving hardware resources and enhancing the flexibility of the system. In this paper, the Xilinx Virtex-6 XC6VSX315T chip is selected, and the ASIP design with reconfigurable function unit is realized on the system platform. The main research work in this paper includes: 1) the research background and significance of this subject are discussed, and a reliable local reconstruction design flow is established. Including the Verilog HDL description of circuit functions, the design of static and dynamic regions, configuration implementation and configuration file verification, etc.) combining with CORDIC theory and method, using pipeline design method, designed the specific circuit of the operation. The design of ASIP with reconfigurable function unit can be realized by shift and addition and subtraction operation, and the error is within the allowable range of the system. The basic operation can be realized according to the requirement of instruction set. The simulation results show that the system can realize the time-sharing reuse of hardware resources and improve the utilization of logic resources.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402

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