發(fā)布時(shí)間：2018-03-29 17:38

  本文選題：電荷泵鎖相環(huán)　切入點(diǎn)：二階開(kāi)關(guān)低通濾波器　出處：《哈爾濱工業(yè)大學(xué)》2015年碩士論文

【摘要】：片上系統(tǒng)(So C)上通常集成了多個(gè)功能模塊,每個(gè)模塊需要不同頻率的時(shí)鐘,而So C上只提供一個(gè)固定的參考晶振來(lái)產(chǎn)生所需時(shí)鐘信號(hào)。因此So C上需要設(shè)計(jì)一款用于時(shí)鐘信號(hào)發(fā)生的鎖相環(huán)(PLL)電路。本文設(shè)計(jì)的用于時(shí)鐘信號(hào)發(fā)生的全集成的電荷泵鎖相環(huán)電路,輸入頻率范圍為5~50MHz,輸出頻率范圍為250~500MHz。本文首先根據(jù)電荷泵鎖相環(huán)基本結(jié)構(gòu)對(duì)其各模塊建立相應(yīng)的數(shù)學(xué)模型,從而建立電荷泵鎖相環(huán)系統(tǒng)整體的數(shù)學(xué)模型,根據(jù)設(shè)計(jì)指標(biāo)完成模型中所涉及的系統(tǒng)參數(shù)的計(jì)算。再對(duì)電荷泵鎖環(huán)相進(jìn)行行為級(jí)建模,代入計(jì)算所得系統(tǒng)參數(shù)完成行為級(jí)仿真驗(yàn)證。接著介紹了電荷泵鎖相環(huán)電路中各模塊電路的設(shè)計(jì)過(guò)程,對(duì)設(shè)計(jì)的各模塊做了大量的仿真和分析。為了改善鎖相環(huán)的鎖定性能,提出了一種二階開(kāi)關(guān)低通濾波器的電路結(jié)構(gòu)。在環(huán)路中用該結(jié)構(gòu)替換傳統(tǒng)的二階環(huán)路濾波器,能起到縮短環(huán)路鎖定時(shí)間的作用。本文同時(shí)對(duì)襯底噪聲引起的鎖相環(huán)輸出抖動(dòng)峰峰值和鎖相環(huán)的輸出相位噪聲進(jìn)行了仿真。本文采用SMIC 0.18μm工藝實(shí)現(xiàn)該鎖相環(huán)電路,并完成版圖設(shè)計(jì)和后仿。PLL輸出中心頻率為500MHz,頻偏為1MHz處PLL輸出相位噪為-97.6901d Bc@1MHz。
[Abstract]:The on-chip system is usually integrated with multiple functional modules, each requiring a different frequency clock, On so C, only a fixed reference crystal oscillator is provided to generate the required clock signal. Therefore, it is necessary to design a PLLL circuit for clock signal generation on so C. The full integration for clock signal generation is designed in this paper. The charge pump PLL circuit, The input frequency range is 5 ~ 50 MHz and the output frequency range is 250 ~ 500 MHz. In this paper, the corresponding mathematical model of each module is established according to the basic structure of the charge pump phase-locked loop (CPPLL), and the whole mathematical model of the charge-pump phase-locked loop (CPPLL) system is established in this paper. According to the design index, the calculation of the system parameters involved in the model is completed, and then the behavior level model of the charge pump phase locking is built. Then the design process of each module circuit in the charge pump phase-locked loop circuit is introduced, and a lot of simulation and analysis are done for each module designed. In order to improve the locking performance of the phase-locked loop, In this paper, a circuit structure of second-order switching low-pass filter is proposed, which is used to replace the traditional second-order loop filter in the loop. This paper simulates the output jitter peak of PLL caused by substrate noise and the output phase noise of PLL. In this paper, SMIC 0.18 渭 m technology is used to realize the PLL circuit. The output center frequency is 500MHz and the output phase noise of PLL is -97.6901d Bc@ 1MHz at 1MHz offset.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN47

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前1條

1 呂郁;自適應(yīng)帶寬時(shí)鐘發(fā)生器的抖動(dòng)一致性研究[D];國(guó)防科學(xué)技術(shù)大學(xué);2009年

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本文編號(hào)：1682147