本文選題：信號(hào)完整性分析　切入點(diǎn)：DDR3內(nèi)存　出處：《華南理工大學(xué)》2015年碩士論文

【摘要】：現(xiàn)代電子技術(shù)的發(fā)展日新月異,從上世紀(jì)六十年代開始,集成電路按照摩爾定律發(fā)展,每隔18個(gè)月可容納晶體管數(shù)目增加-倍,性能也提高一倍。隨著性能不斷提高,集成電路的內(nèi)部運(yùn)行頻率越來越高,片外總線頻率隨之增長(zhǎng)。板載信號(hào)線的頻率不斷提高,給電路設(shè)計(jì)帶來許多信號(hào)完整性方面的問題,如反射、串?dāng)_、振鈴現(xiàn)象等。高速電路的信號(hào)完整性問題,給電路設(shè)計(jì)帶來許多挑戰(zhàn),傳輸線長(zhǎng)度、阻抗、印制板和芯片封裝的不合理設(shè)計(jì)與選擇,都會(huì)對(duì)高速信號(hào)造成影響,使信號(hào)中出現(xiàn)噪聲,進(jìn)而導(dǎo)致信號(hào)失真。文中針對(duì)DDR3設(shè)計(jì)中存在的,拐角阻抗突變、過孔容性負(fù)載、延遲線和元器件封裝等影響DDR3信號(hào)完整性問題進(jìn)行分析,并提出改進(jìn)方案。DDR3不同的布線拓?fù)浣Y(jié)構(gòu)有不同效果,并應(yīng)用在不同場(chǎng)合和信號(hào)頻率。文中詳細(xì)的介紹和分析DDR3布線的各種拓?fù)浣Y(jié)構(gòu),特別是T型拓?fù)洹⒕栈ㄦ溚負(fù)浜虵ly-by拓?fù)�。這三種拓?fù)涠际轻槍?duì)地址/時(shí)鐘/控制信號(hào)的走線拓?fù)?在1GHz信號(hào)頻率情況下三種拓?fù)浣Y(jié)構(gòu)的優(yōu)缺點(diǎn)并不十分明顯。文中分別根據(jù)拓?fù)浣Y(jié)構(gòu)的特點(diǎn)和應(yīng)用環(huán)境,建設(shè)性的提出了三種拓?fù)浣Y(jié)構(gòu)應(yīng)該在什么條件下使用,使DDR3在不同條件下使用最合適的拓?fù)浣Y(jié)構(gòu),優(yōu)化DDR3信號(hào)性能。論文中的電路設(shè)計(jì)方法引入信號(hào)完整性仿真手段。與傳統(tǒng)電路設(shè)計(jì)方法不同,高速電路設(shè)計(jì)很難根據(jù)經(jīng)驗(yàn)判斷信號(hào)的好壞,需要結(jié)合必要的信號(hào)完整性分析方法和仿真手段完成電路設(shè)計(jì)。在PCB布線階段對(duì)電路信號(hào)進(jìn)行仿真分析,直到信號(hào)仿真結(jié)果達(dá)到要求才進(jìn)行下一步生產(chǎn)。高速電路的設(shè)計(jì)方法,不但解決信號(hào)完整性問題,還能縮短電子設(shè)備的設(shè)計(jì)周期,有效的保障硬件設(shè)計(jì)的質(zhì)量和提高生產(chǎn)效率。課題研究在飛思卡爾處理器IMX6電路中DDR3的運(yùn)行情況,探討DDR3電路設(shè)計(jì)中遇到的信號(hào)完整性問題。通過分析對(duì)比DDR3不同的拓?fù)浣Y(jié)構(gòu),提出各拓?fù)浣Y(jié)構(gòu)的應(yīng)用場(chǎng)合,使用仿真手段優(yōu)化DDR3拓?fù)浣Y(jié)構(gòu)和布線方案,提高DDR3的性能和穩(wěn)定性。
[Abstract]:With the rapid development of modern electronic technology, since the 1960s, integrated circuits have been developed in accordance with Moore's law, and the number of transistors can be increased and their performance doubled every 18 months. The frequency of off-chip bus increases with the increasing internal frequency of integrated circuits. The frequency of on-board signal lines is increasing constantly, which brings many problems of signal integrity to the circuit design, such as reflection, crosstalk, etc. The problem of signal integrity of high speed circuit brings many challenges to the circuit design, such as the length of transmission line, impedance, improper design and selection of printed circuit board and chip package, all of which will affect the high speed signal. In this paper, the problems of corner impedance mutation, perforation load, delay line and component package affecting the integrity of DDR3 signal are analyzed. The improved scheme. DDR3 has different effects and is used in different occasions and signal frequencies. The paper introduces and analyzes the various topological structures of DDR3 routing, especially T-type topology. Chrysanthemum chain topology and Fly-by topology. These three topologies are routing topologies for address / clock / control signals, The merits and demerits of the three topologies are not obvious in the case of 1GHz signal frequency. According to the characteristics of the topology and the application environment, this paper constructively proposes the conditions under which the three topologies should be used. Make DDR3 use the most suitable topology under different conditions, and optimize the performance of DDR3 signal. The circuit design method in this paper introduces signal integrity simulation method, which is different from the traditional circuit design method. It is difficult to judge whether the signal is good or bad according to the experience in high-speed circuit design. It is necessary to combine the necessary signal integrity analysis method and simulation method to complete the circuit design. The circuit signal is simulated and analyzed in the stage of PCB wiring. The design method of high-speed circuit not only solves the problem of signal integrity, but also shortens the design period of electronic equipment. This paper studies the operation of DDR3 in IMX6 circuit of Freescale processor, discusses the problem of signal integrity encountered in the design of DDR3 circuit, and analyzes and compares the different topology of DDR3. In order to improve the performance and stability of DDR3, it is proposed that the topology and routing scheme of DDR3 can be optimized by simulation in the applications of various topologies.
【學(xué)位授予單位】：華南理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402

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本文編號(hào)：1679003