本文選題：時間交織模數(shù)轉(zhuǎn)換器　切入點：迭代算法　出處：《合肥工業(yè)大學(xué)》2017年碩士論文

【摘要】：隨著半導(dǎo)體制造工藝的進步,數(shù)字芯片上單片集成度更高,但對于模擬芯片模數(shù)轉(zhuǎn)換器(Analog-to-Digital Converter, ADC)的性能提升并不大,設(shè)計出高速高精度的模數(shù)轉(zhuǎn)換器顯得比較困難,而傳統(tǒng)的模數(shù)轉(zhuǎn)換器已經(jīng)不能滿足人們的需求。時間交織模數(shù)轉(zhuǎn)換器(Time-interleaved Aanlog-to-Digital Converter, TIADC)通過多個ADC并行采樣實現(xiàn)高速度,成為設(shè)計高速度模數(shù)轉(zhuǎn)換器的一種主流架構(gòu)。時間交織模數(shù)轉(zhuǎn)換器通過多個通道并行采樣實現(xiàn)高速度,但由于工藝制造過程中存在工藝失配,嚴重影響了系統(tǒng)的性能。本文主要對通道間存在的三種誤差進行分析,針對失調(diào)誤差,本文提出了一種基于自適應(yīng)迭代的校準算法,該算法通過LMS迭代來估計通道間的失調(diào)誤差,通過待校準通道輸出與參考通道輸出做差,實現(xiàn)誤差的補償;針對增益和采樣時間誤差,本文提出一種基于信號調(diào)制的校準算法,該算法利用信號調(diào)制基本原理使信號主頻點和雜散頻點位置互換并構(gòu)建一個系數(shù)使調(diào)制后主頻點能量幅值與調(diào)制前雜散頻點能量幅值相等,最后消除由增益和采樣時間誤差引入的雜散,通過改進算法中的微分器,實現(xiàn)算法對寬帶寬輸入信號的校準,即算法不受輸入信號頻率的限制。為了驗證算法功能,本文搭建了 4通道12bits 200MHz的時間交織模數(shù)轉(zhuǎn)換器模型,在模型中加入三種誤差,當(dāng)輸入信號的歸一化頻率(fin/fs)分別為0.0197、0.3227和0.8019時,經(jīng)過校準算法后,輸出數(shù)據(jù)的有效位數(shù)分別能達到11.65bits、11.69bits和11.61bits,驗證了算法不同輸入頻段內(nèi)信號的有效性。接著利用verilog語言對算法進行了 RTL代碼的設(shè)計,并在Modelsim中進行了代碼的功能驗證,最后將算法放到FPGA開發(fā)板上做了硬件驗證,同時對算法進行了 DC綜合,形式驗證、功耗分析和自動布局布線等ASIC流程設(shè)計。
[Abstract]:With the progress of semiconductor manufacturing technology, the integration of single chip on digital chip is higher, but the performance of Analog-to-Digital converter (ADCC) is not much improved, so it is difficult to design high speed and high precision ADC. But the traditional analog-to-digital converter can not meet the needs of the people. Time-interleaved Aanlog-to-Digital converter (TIADC) achieves high speed through multiple ADC parallel sampling. Time interleaved ADC achieves high speed through parallel sampling of multiple channels, but due to process mismatch in the process of manufacturing, time interleaved analog-to-digital converter (ADC) has become a mainstream architecture in the design of high speed analog-to-digital converters. In this paper, three kinds of errors between channels are analyzed, and a calibration algorithm based on adaptive iteration is proposed for the misalignment error. The LMS iteration is used to estimate the misalignment error between the channels, and the error compensation is realized by the error between the output of the channel to be calibrated and the output of the reference channel, and a calibration algorithm based on signal modulation is proposed for the error of gain and sampling time. The algorithm uses the basic principle of signal modulation to swap the position between the main frequency point and the stray frequency point, and constructs a coefficient so that the energy amplitude of the main frequency point after modulation is equal to the energy amplitude of the stray frequency point before modulation. Finally, the spurious signal introduced by gain and sampling time error is eliminated. By improving the differentiator in the algorithm, the wide-band input signal is calibrated, that is, the algorithm is not limited by the frequency of the input signal. In this paper, a time-interleaved analog-to-digital converter model of 4-channel 12bits 200MHz is built. Three kinds of errors are added to the model. When the normalized frequency of input signal is 0.0197 / 0.3227 and 0.8019, respectively, after the calibration algorithm, The effective digits of the output data can reach 11.65 bits11.69 bits and 11.61 bitsrespectively, which verify the validity of the algorithm in different input frequency bands. Then, the RTL code is designed by using verilog language, and the function of the code is verified in Modelsim. Finally, the algorithm is applied to the FPGA development board for hardware verification. At the same time, DC synthesis, formal verification, power analysis and automatic layout and routing are used to design the algorithm.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN792

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